On Mon, 14 Oct 2024 08:25:35 +0100 David Woodhouse wrote:
> On Wed, 2024-10-09 at 17:32 -0700, Jakub Kicinski wrote:
> > On Sun, 06 Oct 2024 08:17:58 +0100 David Woodhouse wrote:
> > > +config PTP_1588_CLOCK_VMCLOCK
> > > + tristate "Virtual machine PTP clock"
> > > + depends on X86_T
On 10/14/24 11:02, Michael Tokarev wrote:
On 09.10.2024 03:04, Richard Henderson wrote:
Drop the 'else' so that ret is overridden with the
highest priority fault.
Fixes: d8bc1381250 ("target/hppa: Implement PSW_X")
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: R
On 14.10.2024 18:15, Daniel P. Berrangé wrote:
These two lines are the only place in the code that uses the
char response[40];
so even better than switching to snprintf, how about just taking
buffer size out of the picture:
g_autofree *response =
g_strdup_printf("\033[%d;%dR",
34e5e1 refactored the plugin context initialization. After this change,
tcg_ctx->plugin_insn is not reset inconditionnally anymore, but only if
one plugin at least is active.
When uninstalling the last plugin active, we stopped reinitializing
tcg_ctx->plugin_insn, which leads to memory callbacks b
On 10/14/24 15:01, Paolo Savini wrote:
This patch optimizes the emulation of unit-stride load/store RVV instructions
when the data being loaded/stored per iteration amounts to 64 bytes or more.
The optimization consists of calling __builtin_memcpy on chunks of data of 128
bytes between the memory
MEMOP_IDX() is unused since commit 948f88661c6 ("target/mips:
Use cpu_*_data_ra for msa load/store"), remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_helper.c | 8
1 file changed, 8 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_he
On 10/14/24 15:18, Philippe Mathieu-Daudé wrote:
On 13/10/24 13:05, Richard Henderson wrote:
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
+++ b/target/mips/tcg/msa_helper.c
@@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
#if !defined(CONFIG_
On 10/14/24 15:33, Pierrick Bouvier wrote:
34e5e1 refactored the plugin context initialization. After this change,
tcg_ctx->plugin_insn is not reset inconditionnally anymore, but only if
one plugin at least is active.
When uninstalling the last plugin active, we stopped reinitializing
tcg_ctx->p
On 10/13/24 11:47, Richard Henderson wrote:
Suggested-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 72240
Sent a v2 to fix a leak issue with tcg_ctx->plugin_tb.
On 10/14/24 15:33, Pierrick Bouvier wrote:
34e5e1 refactored the plugin context initialization. After this change,
tcg_ctx->plugin_insn is not reset inconditionnally anymore, but only if
one plugin at least is active.
When uninstalling the
34e5e1 refactored the plugin context initialization. After this change,
tcg_ctx->plugin_insn is not reset inconditionnally anymore, but only if
one plugin at least is active.
When uninstalling the last plugin active, we stopped reinitializing
tcg_ctx->plugin_insn, which leads to memory callbacks b
The REX.W prefix is ignored for these instructions.
Mirror the solution already used for INS/OUTS: X86_SIZE_z.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2581
Signed-off-by: Richard Henderson
---
target/i386/tcg/decode-new.c.inc | 8
1 file changed, 4 insertions(+), 4 delet
If one thread modifies the mappings and another thread prints them,
a situation may occur that the printer thread sees a guest mapping
without a corresponding host mapping, leading to a crash in
open_self_maps_2().
Cc: qemu-sta...@nongnu.org
Fixes: 7b7a3366e142 ("linux-user: Use walk_memory_region
[[ sorry for the lag $LIFE has been over-full lately ]]
On Thu, Oct 3, 2024 at 3:56 AM Alex Bennée wrote:
> Warner Losh writes:
>
> > On Thu, Oct 3, 2024 at 2:53 AM Warner Losh wrote:
> >
> > On Thu, Sep 26, 2024 at 8:24 AM Alex Bennée
> wrote:
> >
> > One output from this discussion should
On 14.10.2024 22:31, Richard Henderson wrote:
On 10/14/24 11:02, Michael Tokarev wrote:
On 09.10.2024 03:04, Richard Henderson wrote:
Drop the 'else' so that ret is overridden with the
highest priority fault.
Fixes: d8bc1381250 ("target/hppa: Implement PSW_X")
Reviewed-by: Helge Deller
Review
Certain CPU architecture specifications [1][2][3] prohibit changes to the CPUs
*presence* after the kernel has booted. This is because many system
initializations depend on the exact CPU count at boot time and do not expect it
to change afterward. For example, components like interrupt controllers
Certain CPU architecture specifications [1][2][3] prohibit changes to CPU
presence after the kernel has booted. This limitation exists because many system
initializations rely on the exact CPU count at boot time and do not expect it to
change later. For example, components like interrupt controller
Update the `AcpiCpuStatus` for `is_enabled` and `is_present` accordingly when
vCPUs are hot-plugged or hot-unplugged, taking into account the *persistence*
of the vCPUs.
Signed-off-by: Salil Mehta
---
hw/acpi/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/acpi/cpu.c b/hw/acp
Reflect the ACPI CPU hotplug `is_{present, enabled}` states in the `_STA.PRES`
(presence) and `_STA.ENA` (enabled) bits when the guest kernel evaluates the
ACPI `_STA` method during initialization, as well as when vCPUs are hot-plugged
or hot-unplugged. The presence of unplugged vCPUs may need to b
The ACPI CPU hotplug states `is_{present, enabled}` must be migrated alongside
other vCPU hotplug states to the destination VM. Therefore, they should be
integrated into the existing CPU Hotplug VM State Description (VMSD) table.
Depending on the architecture and its implementation of CPU hotplug e
Philippe Mathieu-Daudé writes:
> On 10/10/24 16:25, Markus Armbruster wrote:
>> Philippe Mathieu-Daudé writes:
>>
>>> On 10/10/24 12:01, Markus Armbruster wrote:
The error message for a "stepping" value that is out of bounds is a
bit odd:
$ qemu-system-x86_64 -cpu qemu64,st
On Mon, Oct 14, 2024 at 7:10 PM Thomas Huth wrote:
>
> The linker on OpenBSD complains:
>
> ld: warning: console-vc.c:824 (../src/ui/console-vc.c:824)([...]):
> warning: sprintf() is often misused, please use snprintf()
>
> Using snprintf() is certainly better here, so let's switch to that
> fun
Hi Bibo,
> From: maobibo
> Sent: Monday, October 14, 2024 9:53 AM
> To: qemu-devel@nongnu.org; Salil Mehta
> Cc: Michael S. Tsirkin ; Peter Maydell
> ; Salil Mehta ;
> zhukeqian ; Jonathan Cameron
> ; Gavin Shan ;
> Vishnu Pajjuri ; Xianglai Li
> ; Miguel Luis ; Shaoqin
> Huang ; Zhao
Hi Igor,
> From: qemu-devel-bounces+salil.mehta=huawei@nongnu.org devel-bounces+salil.mehta=huawei@nongnu.org> On Behalf Of Igor
> Mammedov
> Sent: Monday, October 14, 2024 10:38 AM
>
> On Mon, 14 Oct 2024 16:52:55 +0800
> maobibo wrote:
>
> > Hi Salil,
> >
> > When I debug
SDL API changes GL context to a newly created GL context, which differs
from other GL providers that don't switch context. Change SDL backend to
restore the original GL context. This allows Qemu's virtio-gpu to support
new virglrenderer async-fencing feature for Virgl contexts, otherwise
virglrende
This patchset adds DRM native context support to VirtIO-GPU on Qemu.
It's based on the pending Venus v17 patches [1] that bring host blobs
support to virtio-gpu-gl device.
Based-on: 20240822185110.1757429-1-dmitry.osipe...@collabora.com
[1]
https://lore.kernel.org/qemu-devel/20240822185110.17574
From: Pierre-Eric Pelloux-Prayer
If EGL is used, we can rely on dmabuf to import textures without
doing copies.
To get this working on X11, we use the existing SDL hint:
SDL_HINT_VIDEO_X11_FORCE_EGL (because dmabuf can't be used with GLX).
Signed-off-by: Pierre-Eric Pelloux-Prayer
Signed-off-b
Update kernel headers to bring new VirtIO-GPU DRM capset.
Signed-off-by: Dmitry Osipenko
---
include/standard-headers/drm/drm_fourcc.h | 43
include/standard-headers/linux/const.h| 17 ++
include/standard-headers/linux/ethtool.h | 226 ++
include/standard-
Support asynchronous fencing feature of virglrenderer. It allows Qemu to
handle fence as soon as it's signalled instead of periodically polling
the fence status. This feature is required for enabling DRM context
support in Qemu because legacy fencing mode isn't supported for DRM
contexts in virglre
Add support for DRM native contexts to VirtIO-GPU. DRM context is enabled
using a new virtio-gpu-gl device option "drm=on".
Unlike Virgl and Venus contexts that operate on application API level,
DRM native contexts work on a kernel UAPI level. This lower level results
in a lightweight context impl
Print out error messages when virgl fence creation fails to aid debugging
of the fence-related bugs.
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-virgl.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-v
On 2024/10/15 03:34, Stewart Hildebrand wrote:
> +Edgar
>
> On 5/16/24 06:13, Jiqian Chen wrote:
>> In PVH dom0, it uses the linux local interrupt mechanism,
>> when it allocs irq for a gsi, it is dynamic, and follow
>> the principle of applying first, distributing first. And
>> the irq number is
Under situation where virtual machine is running in a deployment where
the system time is unstable, there is a chance that legacy OpenStack
Windows machines without stimer enabled will crash if system time moves
backwards and diftfix=slew is enabled. This primarily caused by the fact
the system tim
+Edgar
On 5/16/24 06:13, Jiqian Chen wrote:
> In PVH dom0, it uses the linux local interrupt mechanism,
> when it allocs irq for a gsi, it is dynamic, and follow
> the principle of applying first, distributing first. And
> the irq number is alloced from small to large, but the
> applying gsi numbe
On Sat, 2024-10-12 at 08:20 +0200, Cédric Le Goater wrote:
> + Aspeed reviewers. Sorry about that.
All good. Seems sensible in concept and from a cursory glance, so if
you want to tack it on:
Acked-by: Andrew Jeffery
Hi Salil,
On 2024/10/15 上午3:59, Salil Mehta wrote:
Hi Bibo,
From: maobibo
Sent: Monday, October 14, 2024 9:53 AM
To: qemu-devel@nongnu.org; Salil Mehta
Cc: Michael S. Tsirkin ; Peter Maydell
; Salil Mehta ;
zhukeqian ; Jonathan Cameron
; Gavin Shan ;
Vishnu Pajjuri ; Xianglai
This version 3 of the patch adds endianness safety to both the optimizations
brought by the patch set.
It also adds some conditions that allow the __builtin_memcpy to be executed
on chunks of 16 bytes with guarantee of atomicity.
Changes from V2:
- patch 1:
- add condition for the host not to be
From: Helene CHELIN
This patch improves the performance of the emulation of the RVV unit-stride
loads and stores in the following cases:
- when the data being loaded/stored per iteration amounts to 8 bytes or less.
- when the vector length is 16 bytes (VLEN=128) and there's no grouping of the
This patch optimizes the emulation of unit-stride load/store RVV instructions
when the data being loaded/stored per iteration amounts to 64 bytes or more.
The optimization consists of calling __builtin_memcpy on chunks of data of 128
bytes between the memory address of the simulated vector register
On 10/10/24 05:36, Paolo Bonzini wrote:
It is used in a couple of places only, both within the same target. Those can
use the cflags just as well, so remove the separate field.
Signed-off-by: Paolo Bonzini
---
include/exec/translator.h | 2 --
accel/tcg/translator.c | 1 -
target/mi
On 13/10/24 15:47, Richard Henderson wrote:
This argument is no longer used.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/i386/tcg/sysemu/excp_helper.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Philippe Mathie
On 13/10/24 13:05, Richard Henderson wrote:
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
+++ b/target/mips/tcg/msa_helper.c
@@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env,
uint32_t df, uint32_t wd,
#if !defined(CONFIG_USER_ONLY)
#define
MEMOP_IDX(DF)
On 10/14/24 16:22, Philippe Mathieu-Daudé wrote:
MEMOP_IDX() is unused since commit 948f88661c6 ("target/mips:
Use cpu_*_data_ra for msa load/store"), remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_helper.c | 8
1 file changed, 8 deletions(-)
Reviewed-by:
On 10/9/24 17:50, Pierrick Bouvier wrote:
Eventually fixing the page size > TARGET_PAGE_SIZE performance issues.
E.g. with a 16k or 64k aarch64 guest kernel, we still have TARGET_PAGE_SIZE at
4k, so all
guest pages are "large", and so run into our current behaviour of flushing the
entire tlb
t
With cpu-add/cpu-del command tested on LoongArch system, no migration
tested. There is no negative influence with LoongArch cpu hotplug.
Regards
Bibo Mao
On 2024/10/15 上午3:22, Salil Mehta via wrote:
Certain CPU architecture specifications [1][2][3] prohibit changes to the CPUs
*presence* after
On Fri, Oct 11, 2024 at 11:34:17AM -0400, Peter Xu wrote:
> This reverts two commits:
>
> 671326201dac8fe91222ba0045709f04a8ec3af4
> 1b1f4ab69c41279a45ccd0d3178e83471e6e4ec1
>
> Meanwhile it adds an entry to removed-features.rst for the
> query-migrationthreads QMP command.
>
> This patch origin
Add system test to make sure FEAT_XS is enabled for max cpu emulation
and that QEMU doesn't crash when encountering an NXS instruction
variant.
Signed-off-by: Manos Pitsidianakis
---
tests/tcg/aarch64/system/feat-xs.c | 27 +++
1 file changed, 27 insertions(+)
diff --git
Signed-off-by: Manos Pitsidianakis
---
target/arm/cpu-features.h | 5 +
target/arm/helper.c | 366 +++---
2 files changed, 218 insertions(+), 153 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index
04ce2818263e2c3
This series is an initial incomplete attempt at adding support for the
FEAT_XS feature in aarch64 TCG. This feature was introduced in ARMv8.7:
it adds a new memory attribute XS which indicates that a memory access
could take longer than usual to complete and also adds instruction
variants for TLBI
Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register.
Signed-off-by: Manos Pitsidianakis
---
target/arm/tcg/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index
0168920828651492b1114d66ab0fc72c20dda2a8..8c8f88d84151
The DSB nXS variant is always both a reads and writes request type.
Ignore the domain field like we do in plain DSB and perform a full
system barrier operation.
The DSB nXS variant is part of FEAT_XS made mandatory from Armv8.7.
Signed-off-by: Manos Pitsidianakis
---
target/arm/tcg/a64.decode
>On Mon, 14 Oct 2024 10:32 +0530
> wrote:
>
>On Sat, 14 Sep 2024 16:50:21 +0530
> wrote:
>
>> From: Ajay Joshi
>>
>> The current completion percentage calculation
>> does not account for the relative time since
>> the start of the background activity, this leads
>> to showing incorrect start perc
On Sun, Oct 13, 2024 at 10:32:36PM +0600, Dorjoy Chowdhury wrote:
> Hi,
> I think there maybe some bugs caused by the recent crypto patches that got
> merged to master. ref:
> https://lore.kernel.org/qemu-devel/cafeaca-e_1wflun2hpttt2bszxksmbnxkak_uzuhwrh_fb6...@mail.gmail.com/T/#t
>
> I think bef
On Mon, 14 Oct 2024 at 11:12, Peter Maydell wrote:
>
> On Fri, 11 Oct 2024 at 18:13, Paolo Bonzini wrote:
> > v2->v3: new patches
> > - scripts/archive-source: find directory name for subprojects
> > - docs: fix invalid footnote syntax
> > - docs: avoid footnotes consisting of just URLs
> > - doc
On Mon, Oct 14, 2024 at 12:40 PM Peter Maydell wrote:
>
> On Mon, 14 Oct 2024 at 11:12, Peter Maydell wrote:
> >
> > On Fri, 11 Oct 2024 at 18:13, Paolo Bonzini wrote:
> > > v2->v3: new patches
> > > - scripts/archive-source: find directory name for subprojects
> > > - docs: fix invalid footnote
On Mon, 14 Oct 2024 13:40, Peter Maydell wrote:
>On Mon, 14 Oct 2024 at 11:12, Peter Maydell wrote:
>>
>> On Fri, 11 Oct 2024 at 18:13, Paolo Bonzini wrote:
>> > v2->v3: new patches
>> > - scripts/archive-source: find directory name for subprojects
>> > - docs: fix invalid footnote syntax
>> > -
If the defaults for --enable-rust ($rust in configure) and Meson's rust
option are out of sync, incremental builds will pick Meson's default.
This happens because, on an incremental build, configure does not run
Meson, Make does instead. Meson then gets the command line options
from either coreda
On Mon, Oct 14, 2024 at 11:40:11AM +0100, Peter Maydell wrote:
> On Mon, 14 Oct 2024 at 11:12, Peter Maydell wrote:
> >
> > On Fri, 11 Oct 2024 at 18:13, Paolo Bonzini wrote:
> > > v2->v3: new patches
> > > - scripts/archive-source: find directory name for subprojects
> > > - docs: fix invalid fo
On Thu, 10 Oct 2024 16:08:51 -0700
Fan Ni wrote:
> On Wed, Oct 09, 2024 at 06:41:57PM -0700, Davidlohr Bueso wrote:
> > Add Get/Set Response Message Limit commands.
> >
> > Signed-off-by: Davidlohr Bueso
>
> The commit log may include the cxl spec reference. Otherwise,
>
> Reviewed-by: Fan
Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT,
{H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the
presence of the Ssdbltrp ISA extension.
Signed-off-by: Clément Léger
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_bits.h |
Add the switch to enable the Ssdbltrp ISA extension.
Signed-off-by: Clément Léger
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 65347ccd5a..4a146bb637 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -190,6 +
Add the switch to enable the Smdbltrp ISA extension.
Signed-off-by: Clément Léger
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 53e3bb6b37..6e22bfe37d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -183,6 +
When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared
when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared
when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning
to VU from HS.
Signed-off-by: Clément Léger
---
target/riscv/op_helper.c | 35 +
Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior.
Also set MDT to 1 at reset according to the specification.
Signed-off-by: Clément Léger
---
target/riscv/cpu.c | 3 +++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 15 +
A double trap typically arises during a sensitive phase in trap handling
operations — when an exception or interrupt occurs while the trap
handler (the component responsible for managing these events) is in a
non-reentrant state. This non-reentrancy usually occurs in the early
phase of trap handlin
When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode
while SSTATUS.SDT isn't cleared, generate a double trap exception to
M-mode.
Signed-off-by: Clément Léger
---
target/riscv/cpu.c| 2 +-
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 42 ++
When the Smsdbltrp ISA extension is enabled, if a trap happens while
MSTATUS.MDT is already set, it will trigger an abort or an NMI is the
Smrnmi extension is available.
Signed-off-by: Clément Léger
---
target/riscv/cpu_helper.c | 35 ++-
1 file changed, 26 insert
When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared
when executing sret if executed in M-mode. When executing mret/mnret,
SSTATUS.MDT is cleared.
Signed-off-by: Clément Léger
---
target/riscv/op_helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/ri
On Fri, 11 Oct 2024 13:24:50 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> One DC extent add/release request can take multiple DC extents.
> For each extent in the request, one DC event record will be generated and
> isnerted into the event log. All the event records for the request will b
On Wed, 2024-10-09 at 17:32 -0700, Jakub Kicinski wrote:
> On Sun, 06 Oct 2024 08:17:58 +0100 David Woodhouse wrote:
> > +config PTP_1588_CLOCK_VMCLOCK
> > + tristate "Virtual machine PTP clock"
> > + depends on X86_TSC || ARM_ARCH_TIMER
> > + depends on PTP_1588_CLOCK && ACPI &&
On 11/10/2024 13:38, Daniel Henrique Barboza wrote:
> Hi Tommy,
>
>
> Do you plan to send a new version of this work soon? This series is a
> prerequisite
> of "target/riscv: Add support for Smdbltrp and Ssdbltrp extensions" and
> we need
> this series merged first. We have minor comments from
On 11/10/2024 05:22, Alistair Francis wrote:
> On Wed, Sep 25, 2024 at 9:59 PM Clément Léger wrote:
>>
>> When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode
>> while SSTATUS.SDT isn't cleared, generate a double trap exception to
>> M-mode.
>>
>> Signed-off-by: Clément Léger
On 11/10/2024 05:24, Alistair Francis wrote:
> On Wed, Sep 25, 2024 at 9:59 PM Clément Léger wrote:
>>
>> Add the switch to enable the Ssdbltrp ISA extension.
>>
>> Signed-off-by: Clément Léger
>> ---
>> target/riscv/cpu.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/target/r
On Wed, 20 Sep 2023 09:36:34 -0500
Corey Minyard wrote:
> On Wed, Sep 20, 2023 at 06:31:25AM -0700, Klaus Jensen wrote:
> > On Sep 20 07:54, Corey Minyard wrote:
> > > On Wed, Sep 20, 2023 at 12:48:03PM +0100, Jonathan Cameron via wrote:
> > > > On Thu, 14 Sep 2023 11:53:40 +0200
> > > > Klau
On Mon, 14 Oct 2024 16:52:55 +0800
maobibo wrote:
> Hi Salil,
>
> When I debug cpu hotplug on LoongArch system, It reports error like this:
> ACPI BIOS Error (bug): Could not resolve symbol [\_SB.GED.CSCN],
> AE_NOT_FOUND
> ACPI Error: Aborting method \_SB.GED._EVT due to previous err
Hello Akihiko,
On 10/12/24 13:05, Akihiko Odaki wrote:
On 2024/10/11 0:44, Cédric Le Goater wrote:
Hello Akihiko,
Sorry for the late reply.
On 9/18/24 17:32, Akihiko Odaki wrote:
On 2024/09/18 17:02, Cédric Le Goater wrote:
Hello,
On 9/13/24 05:44, Akihiko Odaki wrote:
VFs are automatical
Hi Salil,
When I debug cpu hotplug on LoongArch system, It reports error like this:
ACPI BIOS Error (bug): Could not resolve symbol [\_SB.GED.CSCN],
AE_NOT_FOUND
ACPI Error: Aborting method \_SB.GED._EVT due to previous error
(AE_NOT_FOUND)
acpi-ged ACPI0013:00: IRQ method executio
Vitaly Kuznetsov writes:
> Vitaly Kuznetsov writes:
>
>> Changes since '[PATCH RESEND v3 0/3] i386: Fix Hyper-V Gen1 guests stuck
>> on boot with 'hv-passthrough':
>>
>> - Added "target/i386: Make sure SynIC state is really updated before
>> KVM_RUN"
>> to the set.
>>
>> This is a long pe
Clément Léger 於 2024年10月14日 週一 下午3:36寫道：
>
>
>
> On 11/10/2024 13:38, Daniel Henrique Barboza wrote:
> > Hi Tommy,
> >
> >
> > Do you plan to send a new version of this work soon? This series is a
> > prerequisite
> > of "target/riscv: Add support for Smdbltrp and Ssdbltrp extensions" and
> > we n
On Mon, 14 Oct 2024 at 02:13, Andrew Randrianasulu
wrote:
>
> some 8 years ago this patch was sent to qemu-devel:
>
> https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg05333.html
> "[Qemu-devel] [PATCH 7/7] Add ALSA ioctls"
>
> I wonder why it was rejected, may be as part of series?
Hard
Hello Dan,
On 10/14/24 02:08, dan tan wrote:
Hi Cédric,
Thank you for the review comments. Please see my response below.
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-09-12 12:20, Cédric Le Goater wrote:
Hello Dan,
On 9/12/24 18:09, dan ta
On 14/10/2024 11.06, Peter Maydell wrote:
On Mon, 14 Oct 2024 at 02:13, Andrew Randrianasulu
wrote:
some 8 years ago this patch was sent to qemu-devel:
https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg05333.html
"[Qemu-devel] [PATCH 7/7] Add ALSA ioctls"
I wonder why it was rejected
Hi Akihiko,
On 04/06/2024 09:37, Jason Wang wrote:
From: Akihiko Odaki
Multiqueue usage is not negotiated yet when realizing. If more than
one queue is added and the guest never requests to enable multiqueue,
the extra queues will not be deleted when unrealizing and leak.
Fixes: f9d6dbf0bf6e
ping
On Tue, Jul 30, 2024 at 04:15:52PM +0200, Alberto Garcia wrote:
> This tool converts a disk image to qcow2, writing the result directly
> to stdout. This can be used for example to send the generated file
> over the network.
Frontends can be attached and detached during run-time (although detach
is not implemented, but will follow). Counter variable of muxes is not
enough for proper attach/detach management, so this patch implements
bitset: if bit is set for the `mux_bitset` variable, then frontend
device can be found
There is no sense to keep `focus`, `mux_cnt`, `prod`, `cons`
and `tag` variables as signed, those represent either size,
either position in array, which both are unsigned.
`focus` member of `MuxChardev` is kept signed, because initially
set to -1.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lur
Those are boolean variables, not signed integers.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
chardev/char-mux.c | 10 +-
chardev/chardev-internal.h | 4 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/chardev/char-mux.
On Mon, 14 Oct 2024 at 12:01, Paolo Bonzini wrote:
>
> If the defaults for --enable-rust ($rust in configure) and Meson's rust
> option are out of sync, incremental builds will pick Meson's default.
>
> This happens because, on an incremental build, configure does not run
> Meson, Make does instea
Hi Marc-André,
On Thu, Oct 10, 2024 at 12:20 PM Marc-André Lureau
wrote:
>
> Hi Roman
>
> On Thu, Oct 10, 2024 at 1:28 PM Roman Penyaev wrote:
>>
>> `mux_cnt` struct member never goes negative or decrements,
>> so mux chardev can be !busy only when there are no
>> frontends attached. This patch
Frontend device can be detached in run-time, which can lead to a
"Chardev 'MUX' is busy" error (see the last patch with the test case
implementation). This series implements frontend detach for the
multiplexer based on bitset, which provides the ability to attach or
detach frontend devices in any o
`mux_cnt` struct member never goes negative or decrements,
so mux chardev can be !busy only when there are no
frontends attached. This patch fixes the always-true
check.
Fixes: a4afa548fc6d ("char: move front end handlers in CharBackend")
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc:
This patch tests:
1. feasibility of removing mux which does not have frontends attached
or frontends were prior detached.
2. inability to remove mux which has frontends attached (mux is "busy")
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
tests/unit/tes
Clean up forgotten leftovers.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
chardev/chardev-internal.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/chardev/chardev-internal.h b/chardev/chardev-internal.h
index 4e03af31476c..c3024b51fdda 100644
--- a/ch
Move away logic which attaches frontend device to a mux
from `char-fe.c` to actual `char-mux.c` implementation
and make it a separate function.
No logic changes are made.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
chardev/char-fe.c | 9 +---
With bitset management now it becomes feasible to implement
the logic of detaching frontends from multiplexer.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
chardev/char-fe.c | 2 +-
chardev/char-mux.c | 20 +---
chardev/cha
On Mon, 14 Oct 2024 11:09:12 +0100
Jonathan Cameron via wrote:
> On Fri, 27 Sep 2024 10:17:43 +0100
> wrote:
>
> > From: Shiju Jose
> >
> > CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
> > control feature.
> >
> > ECS log capabilities field in following ECS ta
On Sun, 13 Oct 2024 at 23:20, Richard Henderson
wrote:
>
> The following changes since commit 7e3b6d8063f245d27eecce5aabe624b5785f2a77:
>
> Merge tag 'crypto-fixes-pull-request' of https://gitlab.com/berrange/qemu
> into staging (2024-10-10 18:05:43 +0100)
>
> are available in the Git repositor
From: Dmitry Frolov
The sum offset + length may overflow uint32. Since this sum is
compared with uint64_t return value of get_lsa_size(), it makes
sense to choose uint64_t type for offset and length.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 3ebe676a3463 ("hw/cxl/
From: Yao Xingtao
When injecting a new poisoned region through qmp_cxl_inject_poison(),
the newly injected region should not overlap with existing poisoned
regions.
The current validation method does not consider the following
overlapping region:
┌───┬───┬───┐
│a │ b(a) │a │
└───┴───┴
From: Ajay Joshi
The current completion percentage calculation does not account for the
relative time since the start of the background activity, this leads to
showing incorrect start percentage vs what has actually been completed.
This patch calculates the percentage based on the actual elapsed
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