Akshat-Oke wrote:
ping
https://github.com/llvm/llvm-project/pull/109937
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https://github.com/llvm/llvm-project/pull/111634
>From 8e7f36627516a76d76ac7bb1d8c756261b6bbc5c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/2] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm
https://github.com/Akshat-Oke edited
https://github.com/llvm/llvm-project/pull/111634
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@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
Akshat-O
https://github.com/Akshat-Oke edited
https://github.com/llvm/llvm-project/pull/110229
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https://github.com/llvm/llvm-project/pull/110229
>From 2b877142d7a9346033d02e5a977d2dcaa440258c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/7] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm
https://github.com/Akshat-Oke created
https://github.com/llvm/llvm-project/pull/111634
None
>From 2b877142d7a9346033d02e5a977d2dcaa440258c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH] [MIR] Add missing noteNewVirtualRegister callbacks
---
ll
Akshat-Oke wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/111634?utm_source=stack-comment-downstack-mergeability-warnin
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/111634
>From 8e7f36627516a76d76ac7bb1d8c756261b6bbc5c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From f4a65dea10cd581aada8cbdf33dae5a66518ddcf Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/7] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/A
optimisan wrote:
Also updated in PR.
Initializes correct dependency as VirtRegMapWrapper is unused here
https://github.com/llvm/llvm-project/pull/109937
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From b337b06e2ecd3d6bbf740ee9ec857463f32d0f1c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/l
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From 2cefaf6d479b6c7ae6bc8a2267f8e4fee274923c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109938
>From d4cc049c53df27919103625417730595fc2183d7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From af1a1f15867edef93e69c43037a19ab69e8ec2e3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/l
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From 2cefaf6d479b6c7ae6bc8a2267f8e4fee274923c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111357
>From dbc51871aab3d4b5d7d64ef78f2df7833359b17f Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/110229
>From 9ef4d7c5293076be21240a1e8e696b8e1b58d2ff Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/8] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AM
optimisan wrote:
### Merge activity
* **Oct 14, 4:57 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/110229).
https://github.com/llvm/llvm-project/pull/110229
__
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -verify-mac
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -verify-mac
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109937
>From ca685074a7f8bfc75e40dd8172ce9e731e991f4d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 06:35:43 +
Subject: [PATCH] Update correct dependency
Replace unused analysis (VirtRegMap) d
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/110229
>From 671b3c6b33c27374b33eefc4bb20a94aa803f65c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/8] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AM
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111634
>From ccb60e8277d3beeeffba72349ba0f1ffdb21b0fa Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/2] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/110229
>From 6789308b56f950b89ca1ce822f071e3b499b2924 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/8] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AM
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111634
>From 4d77407b08def09e2ff8e5b87bbce46630271e50 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/2] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/
@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
Akshat-O
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From 1cbc26fe2de38ae4e174aec128b39c899dab9136 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/5] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/A
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+
@@ -57,15 +59,21 @@ class LiveRegMatrix : public MachineFunctionPass {
unsigned RegMaskVirtReg = 0;
BitVector RegMaskUsable;
- // MachineFunctionPass boilerplate.
- void getAnalysisUsage(AnalysisUsage &) const override;
- bool runOnMachineFunction(MachineFunction &) ove
https://github.com/Akshat-Oke edited
https://github.com/llvm/llvm-project/pull/109938
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https://github.com/llvm/llvm-project/pull/109939
>From 786fb970b7b1d12a6c6c6888d2b5cfe51363287d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/
https://github.com/Akshat-Oke edited
https://github.com/llvm/llvm-project/pull/109938
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https://github.com/llvm/llvm-project/pull/109963
>From 58fd5012dabc79c87b2b69a2a4d32d655215f144 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU
https://github.com/Akshat-Oke edited
https://github.com/llvm/llvm-project/pull/111357
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https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109938
>From 15692bd09ad90b2bedb7383a9acdb2b3b12453c6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH 1/5] [CodeGen] LiveIntervalUnions::Array Implement move
construc
Akshat-Oke wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/111357?utm_source=stack-comment-downstack-mergeability-warnin
https://github.com/Akshat-Oke created
https://github.com/llvm/llvm-project/pull/111357
None
>From 15692bd09ad90b2bedb7383a9acdb2b3b12453c6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constr
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109937
>From 7b68d9fb711d73319d97abb2c03dac31956f1fa5 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 06:35:43 +
Subject: [PATCH] Update correct dependency
---
llvm/lib/Target/AMDGPU/SILowerSG
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
Akshat-Oke wrote:
Negative test is now in MIR/Generic.
https://github.com/llvm/llvm-project/pull/110229
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@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
Akshat-O
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109937
>From dee5a2949f9b9a3bafef4062bc3c87524cfa73a3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 06:35:43 +
Subject: [PATCH] [AMDGPU][SILowerSGPRSpills] Update the correct pass
dependency
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111357
>From 709adf06299bd730628800ee45ee782faf76c1fe Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From 82eae1421ad7c883b9e6e7696357ff22ba6cad90 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/l
optimisan wrote:
I think this describes it better?
https://github.com/llvm/llvm-project/pull/109937
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109938
>From 679194b945345f0492a540254af5818be2b372fc Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From de0c637b3ba6d431e6b491b1eee52c3f0488333c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109939
>From 839e0c12abe69f277810ff04be823c4fa07e4af3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109937
>From a1925ae960ca3c8637ebb9a7bf7085dc787ee438 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 06:35:43 +
Subject: [PATCH] Update correct dependency
Replace unused analysis dependency wi
https://github.com/Akshat-Oke edited
https://github.com/llvm/llvm-project/pull/109937
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https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109938
>From 60e7f83fe680b04e3cb7c8e2e7bb2383fa0fdded Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/includ
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/109963
>From 241cefb63e69298c0122b3aa7dcf2bcde7426c06 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/111357
>From 47bb19208ed2de82109eb160ba6177b7f888be26 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
@@ -578,3 +578,18 @@ body: |
SI_RETURN
...
+---
Akshat-Oke wrote:
I've put it in the generic test
llvm/test/CodeGen/MIR/Generic/register-flag-error.mir
https://github.com/llvm/llvm-project/pull/110229
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From 1cbc26fe2de38ae4e174aec128b39c899dab9136 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/4] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/A
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From 80207b7bd00d4b0889918d9a7df627f7c304bd7d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/3] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/A
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111357
>From c2a3cdc01eb492f341fce3d8580643003579880b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
optimisan wrote:
### Merge activity
* **Oct 22, 5:41 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/109938).
https://github.com/llvm/llvm-project/pull/109938
__
optimisan wrote:
### Merge activity
* **Oct 22, 5:41 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/109939).
https://github.com/llvm/llvm-project/pull/109939
__
optimisan wrote:
### Merge activity
* **Oct 22, 5:41 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/109937).
https://github.com/llvm/llvm-project/pull/109937
__
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109938
>From dcf4acd796468d093be999c2bd7d9b53b102ba61 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -verify-mac
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109938
>From 38940e946a1331426c99e095d26fe81fd2e34eb9 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From 6cf96bb203bc97862ac38776db14365fc75b451f Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109937
>From db91ca05946f4bd1067819f788edc45c360ef9d7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 06:35:43 +
Subject: [PATCH] [AMDGPU][SILowerSGPRSpills] Correct pass dependency
Replace the
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/111357
>From 052c8b15b41b091cc5b91b41f5dee07f26ccd055 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 7 Oct 2024 08:42:24 +
Subject: [PATCH] [CodeGen] LiveIntervalUnions::Array Implement move
constructor
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From a94c78f1fb0de895fa153fe4948689e4523b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/l
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/109937
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https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/109937
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114010
>From 5f42368e15bdba242c15f9f4493b88f80a8f09b7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 29 Oct 2024 07:14:30 +
Subject: [PATCH] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM
---
.
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109937
>From 2cd5b9b848a13653fe8c42429932f598cd75e763 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 06:35:43 +
Subject: [PATCH] [AMDGPU] Correct pass dependencies for SILowerSGPRSpills
Replace
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From 79e5246844aed5c91b450f866a8862feb9577fa2 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/l
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109939
>From 79e5246844aed5c91b450f866a8862feb9577fa2 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 11:41:18 +
Subject: [PATCH 1/2] [NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
---
llvm/l
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109938
>From dcf4acd796468d093be999c2bd7d9b53b102ba61 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 24 Sep 2024 09:07:04 +
Subject: [PATCH 1/4] [NewPM][CodeGen] Port LiveRegMatrix to NPM
---
llvm/include
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/109963
>From b86a822c6eb4c7080eb45cde7a71da76346e19c7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 25 Sep 2024 11:21:04 +
Subject: [PATCH 1/2] [AMDGPU] Add tests for SIPreAllocateWWMRegs
---
.../AMDGPU/
optimisan wrote:
### Merge activity
* **Oct 22, 5:41 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/109963).
https://github.com/llvm/llvm-project/pull/109963
__
optimisan wrote:
### Merge activity
* **Oct 22, 5:41 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/111357).
https://github.com/llvm/llvm-project/pull/111357
__
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/113874
>From 7394bab5609ec2dc56f1851143d8eebb4a5f5b63 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 28 Oct 2024 06:22:49 +
Subject: [PATCH 1/3] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM
---
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/114010
None
>From f84d99b53730031fef705949a5fd34283e9e9eeb Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 29 Oct 2024 07:14:30 +
Subject: [PATCH] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM
optimisan wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/114010?utm_source=stack-comment-downstack-mergeability-warning
@@ -1,5 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra -print-regusage -o
/dev/null 2>&1 < %s | FileCheck %s
+
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=irtranslator -o - %s \
--
https://github.com/optimisan ready_for_review
https://github.com/llvm/llvm-project/pull/114010
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114010
>From 53067f5276ce2b4ae7a918cf732f5659c35ed81d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 29 Oct 2024 07:14:30 +
Subject: [PATCH 1/2] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM
--
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/113874
>From a95b69c07c7804d2e2a10b939a178a191643a41c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 28 Oct 2024 06:22:49 +
Subject: [PATCH 1/4] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM
---
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114746
>From dcf8feee9c8d410b42fa8bed29a15c14bb7d6d2e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 4 Nov 2024 06:58:14 +
Subject: [PATCH] [CodeGen] Move EnableSinkAndFold to TargetOptions
---
llvm/inclu
@@ -95,12 +107,29 @@ static const Function *findCalledFunction(const Module &M,
return nullptr;
}
-bool RegUsageInfoPropagation::runOnMachineFunction(MachineFunction &MF) {
- const Module &M = *MF.getFunction().getParent();
+bool RegUsageInfoPropagationLegacy::runOnMachineF
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/114010
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/113874
>From a95b69c07c7804d2e2a10b939a178a191643a41c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 28 Oct 2024 06:22:49 +
Subject: [PATCH 1/5] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM
---
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114010
>From 9792d73efca78fc55a9d25afb17448c7aeb490c6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 29 Oct 2024 07:14:30 +
Subject: [PATCH 1/3] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM
--
optimisan wrote:
The default value is false, but two targets are setting it to true.
Currently MachineSink is added by generic TargetPassConfig. Can add the option
to `CGPassBuilderOptions` so targets can set it there instead.
https://github.com/llvm/llvm-project/pull/114746
__
https://github.com/optimisan closed
https://github.com/llvm/llvm-project/pull/114746
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https://github.com/llvm/llvm-project/pull/114745
>From e7e38bc2bce6add242f8af0d2a1d942fdecab3ed Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 30 Oct 2024 04:59:30 +
Subject: [PATCH] [CodeGen][NewPM] Port MachineCycleInfo to NPM
---
.../llvm/Code
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/114746
>From 4e815d99d6c214f0780d70224559a5eb7504cdc6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 4 Nov 2024 06:58:14 +
Subject: [PATCH] [CodeGen] Move EnableSinkAndFold to TargetOptions
---
llvm/inclu
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/114745
None
>From 431e6371f161d0f85c598c789902976e3fa74162 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 30 Oct 2024 04:59:30 +
Subject: [PATCH] [CodeGen][NewPM] Port MachineCycleInfo to NPM
---
.../llv
optimisan wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/114745?utm_source=stack-comment-downstack-mergeability-warning
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