https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/172793
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melver wrote:
@fmayer @vitalybuka - do the names look reasonable to you?
Thanks!
https://github.com/llvm/llvm-project/pull/172030
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https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/172030
>From d4f149dbb21fd7f5e706560b1aa3b8f0b9fa5ae9 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Fri, 12 Dec 2025 17:18:15 +0100
Subject: [PATCH 1/2] tweak test
Created using spr 1.3.8-beta.1
---
clang/test/Code
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/172030
>From d4f149dbb21fd7f5e706560b1aa3b8f0b9fa5ae9 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Fri, 12 Dec 2025 17:18:15 +0100
Subject: [PATCH 1/2] tweak test
Created using spr 1.3.8-beta.1
---
clang/test/Code
@@ -123,26 +124,41 @@ static bool lowerAllowChecks(Function &F, const
BlockFrequencyInfo &BFI,
switch (ID) {
case Intrinsic::allow_ubsan_check:
case Intrinsic::allow_runtime_check: {
- ++NumChecksTotal;
-
bool ToRemove = ShouldRemove(II);
Repla
https://github.com/ramosian-glider approved this pull request.
https://github.com/llvm/llvm-project/pull/172029
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https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/172030
>From d4f149dbb21fd7f5e706560b1aa3b8f0b9fa5ae9 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Fri, 12 Dec 2025 17:18:15 +0100
Subject: [PATCH 1/2] tweak test
Created using spr 1.3.8-beta.1
---
clang/test/Code
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/172030
>From d4f149dbb21fd7f5e706560b1aa3b8f0b9fa5ae9 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Fri, 12 Dec 2025 17:18:15 +0100
Subject: [PATCH 1/2] tweak test
Created using spr 1.3.8-beta.1
---
clang/test/Code
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/172029
>From 7c8dbba4f20841f2759fb7ee9a7c012facf056ac Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Thu, 18 Dec 2025 12:05:08 +0100
Subject: [PATCH] fix
Created using spr 1.3.8-beta.1
---
llvm/lib/Transforms/Instru
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172794
>From 2069a0869ecd304aadebc71ed6b038a012aec376 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:00:27 +0530
Subject: [PATCH] [NPM] Remove "LowerConstantIntrinsicsPass" from the pipeline
---
l
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172795
>From 82805bc6ac48375d4f18fd3810cb7e4a7a56 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:17:49 +0530
Subject: [PATCH] [NPM] Update OptimizedRegAlloc and MachineLateOptimization
pipeline
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172796
>From ef5f9507ae7795d273d14b991a1f36572f3c6328 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:28:47 +0530
Subject: [PATCH] [AMDGPU][NPM] Disable few non useful passes
---
llvm/lib/Target/AM
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172793
>From a1e46965396fefcf12645e376c202839cfc3af56 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 14:51:08 +0530
Subject: [PATCH] [AMDGPU][NPM] add "addPostBBSections()" to NPM
---
llvm/include/ll
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172794
>From 2069a0869ecd304aadebc71ed6b038a012aec376 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:00:27 +0530
Subject: [PATCH] [NPM] Remove "LowerConstantIntrinsicsPass" from the pipeline
---
l
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172793
>From a1e46965396fefcf12645e376c202839cfc3af56 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 14:51:08 +0530
Subject: [PATCH] [AMDGPU][NPM] add "addPostBBSections()" to NPM
---
llvm/include/ll
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172796
>From ef5f9507ae7795d273d14b991a1f36572f3c6328 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:28:47 +0530
Subject: [PATCH] [AMDGPU][NPM] Disable few non useful passes
---
llvm/lib/Target/AM
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172795
>From 82805bc6ac48375d4f18fd3810cb7e4a7a56 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:17:49 +0530
Subject: [PATCH] [NPM] Update OptimizedRegAlloc and MachineLateOptimization
pipeline
https://github.com/c8ef edited https://github.com/llvm/llvm-project/pull/172645
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https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172796
>From 9595ea731e7eb243cc1777e33fb0732d68bd4fa5 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:28:47 +0530
Subject: [PATCH] [AMDGPU][NPM] Disable few non useful passes
---
llvm/lib/Target/AM
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172794
>From 5a8d3b2edb0e61d6cafde1d3b84d35ce09aeb386 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:00:27 +0530
Subject: [PATCH] [NPM] Remove "LowerConstantIntrinsicsPass" from the pipeline
---
l
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172793
>From 867d24508715755011000841ce6f2a5b24bc8f3e Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 14:51:08 +0530
Subject: [PATCH] [AMDGPU][NPM] add "addPostBBSections()" to NPM
---
llvm/include/ll
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172795
>From 5e0c6385e708a7249d7bda256010890acd2c1c6c Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:17:49 +0530
Subject: [PATCH] [NPM] Update OptimizedRegAlloc and MachineLateOptimization
pipeline
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172796
>From 9595ea731e7eb243cc1777e33fb0732d68bd4fa5 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:28:47 +0530
Subject: [PATCH] [AMDGPU][NPM] Disable few non useful passes
---
llvm/lib/Target/AM
wangpc-pp wrote:
The current result on llvm-testsuite of this approach(compiled with `-O3
-march=rva23u64 -mrvv-vector-bits=128`, `-mrvv-vector-bits` is specified to
increase the opportunities of vectorization):
```
Metric:
riscv-insert-vsetvli.NumInsertedVSETVL,riscv-instr-info.NumVRegSpilled
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172794
>From 5a8d3b2edb0e61d6cafde1d3b84d35ce09aeb386 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:00:27 +0530
Subject: [PATCH] [NPM] Remove "LowerConstantIntrinsicsPass" from the pipeline
---
l
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172793
>From 867d24508715755011000841ce6f2a5b24bc8f3e Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 14:51:08 +0530
Subject: [PATCH] [AMDGPU][NPM] add "addPostBBSections()" to NPM
---
llvm/include/ll
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/172795
>From 5e0c6385e708a7249d7bda256010890acd2c1c6c Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Wed, 17 Dec 2025 15:17:49 +0530
Subject: [PATCH] [NPM] Update OptimizedRegAlloc and MachineLateOptimization
pipeline
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/172793
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https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/172795
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ramosian-glider wrote:
LGTM
https://github.com/llvm/llvm-project/pull/172030
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Meinersbur wrote:
Not this year anymore, our operations would not be able to react before the
holidays if something goes wrong. After that, it depends on @petrhosek's
review. I don't know whether they will have larger change requests. It's been
NFC only so fat.
Changes made are responding to
mjklemm wrote:
I'm fine with the PR, consider the comments to be nitpicking.
https://github.com/llvm/llvm-project/pull/171825
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mjklemm wrote:
GitHub messed this comment up. It's meant to be a change to the string of the
error message in that line.
https://github.com/llvm/llvm-project/pull/171825
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mjklemm wrote:
```suggestion
"dimension values can only be specified with 'dims' modifier");
```
https://github.com/llvm/llvm-project/pull/171825
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@@ -1974,6 +1974,10 @@ convertOmpTeams(omp::TeamsOp op, llvm::IRBuilderBase
&builder,
return op.emitError("Lowering of num_teams with dims modifier is NYI.");
}
+ if (op.hasThreadLimitDimsModifier()) {
+return op.emitError("Lowering of thread_limit with dims modifi
@@ -2887,6 +2887,9 @@ convertOmpParallel(omp::ParallelOp opInst,
llvm::IRBuilderBase &builder,
if (auto ifVar = opInst.getIfExpr())
ifCond = moduleTranslation.lookupValue(ifVar);
llvm::Value *numThreads = nullptr;
+ // num_threads dims and values are not yet supported
@@ -2601,14 +2604,39 @@ static LogicalResult verifyPrivateVarList(OpType &op) {
return success();
}
+// Helper: Verify num_threads clause
+LogicalResult
+verifyNumThreadsClause(Operation *op,
+ std::optional numThreadsNumDims,
+ Op
@@ -5654,6 +5657,9 @@ extractHostEvalClauses(omp::TargetOp targetOp, Value
&numThreads,
llvm_unreachable("unsupported host_eval use");
})
.Case([&](omp::ParallelOp parallelOp) {
+// num_threads dims and values are not yet supported
@@ -5774,8 +5780,12 @@ initTargetDefaultAttrs(omp::TargetOp targetOp, Operation
*capturedOp,
threadLimit = teamsOp.getThreadLimit();
}
-if (auto parallelOp = castOrGetParentOfType(capturedOp))
+if (auto parallelOp = castOrGetParentOfType(capturedOp)) {
+
hazzlim wrote:
Nit: use imperative present tense for commit message, i.e. `Added support for
sli/sri intrinsics` -> `Add support for sli/sri intrinsics`
https://github.com/llvm/llvm-project/pull/171448
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@@ -1069,16 +1069,55 @@ class OpenMP_NumThreadsClauseSkip<
> : OpenMP_Clause {
let arguments = (ins
+ConfinedAttr, [IntPositive]>:$num_threads_num_dims,
+Variadic:$num_threads_dims_values,
Optional:$num_threads
kparzysz wrote:
I think we should
https://github.com/abhina-sree updated
https://github.com/llvm/llvm-project/pull/169803
>From 16f3faac450b16cb527e409339fd32b42cc0ad43 Mon Sep 17 00:00:00 2001
From: Abhina Sreeskantharajan
Date: Mon, 24 Nov 2025 11:00:04 -0500
Subject: [PATCH 1/4] add ParserConversionAction
(cherry picked fro
https://github.com/abhina-sree updated
https://github.com/llvm/llvm-project/pull/169803
>From 16f3faac450b16cb527e409339fd32b42cc0ad43 Mon Sep 17 00:00:00 2001
From: Abhina Sreeskantharajan
Date: Mon, 24 Nov 2025 11:00:04 -0500
Subject: [PATCH 1/3] add ParserConversionAction
(cherry picked fro
c8ef wrote:
### Merge activity
* **Dec 18, 3:02 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.com/github/pr/llvm/llvm-project/172645).
https://github.com/llvm/llvm-project/pull/172645
___
c8ef wrote:
### Merge activity
* **Dec 18, 3:02 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.com/github/pr/llvm/llvm-project/172643).
https://github.com/llvm/llvm-project/pull/172643
___
c8ef wrote:
### Merge activity
* **Dec 18, 3:02 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.com/github/pr/llvm/llvm-project/172498).
https://github.com/llvm/llvm-project/pull/172498
___
c8ef wrote:
### Merge activity
* **Dec 18, 3:02 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.com/github/pr/llvm/llvm-project/172312).
https://github.com/llvm/llvm-project/pull/172312
___
c8ef wrote:
### Merge activity
* **Dec 18, 3:02 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.com/github/pr/llvm/llvm-project/172646).
https://github.com/llvm/llvm-project/pull/172646
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cdevadas wrote:
This PR stack is essential for fixing multiple issues. Can we get this stack
merged?
https://github.com/llvm/llvm-project/pull/117544
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https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/172615
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/170329
>From 78c30697352a8d115391b0b66cd51873fa154e81 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 24 Nov 2025 13:48:45 -0500
Subject: [PATCH] StackProtector: Use LibcallLoweringInfo analysis
---
llvm/lib/
@@ -9709,6 +9709,30 @@ unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register
SrcReg,
return AMDGPU::COPY;
}
+bool SIInstrInfo::canAddToBBProlog(const MachineInstr &MI) const {
+ uint16_t Opcode = MI.getOpcode();
+ // Check if it is SGPR spill or wwm-register spill Opcode
https://github.com/pcc approved this pull request.
https://github.com/llvm/llvm-project/pull/160901
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https://github.com/abhina-sree updated
https://github.com/llvm/llvm-project/pull/169803
>From 16f3faac450b16cb527e409339fd32b42cc0ad43 Mon Sep 17 00:00:00 2001
From: Abhina Sreeskantharajan
Date: Mon, 24 Nov 2025 11:00:04 -0500
Subject: [PATCH 1/3] add ParserConversionAction
(cherry picked fro
@@ -9709,6 +9709,30 @@ unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register
SrcReg,
return AMDGPU::COPY;
}
+bool SIInstrInfo::canAddToBBProlog(const MachineInstr &MI) const {
+ uint16_t Opcode = MI.getOpcode();
+ // Check if it is SGPR spill or wwm-register spill Opcode
Author: Valentin Clement (バレンタイン クレメン)
Date: 2025-12-18T11:11:01-08:00
New Revision: 50e88351f8debca0a734c9a0ca784bb86a455bf3
URL:
https://github.com/llvm/llvm-project/commit/50e88351f8debca0a734c9a0ca784bb86a455bf3
DIFF:
https://github.com/llvm/llvm-project/commit/50e88351f8debca0a734c9a0ca784
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/172794
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/170329
>From aee9d14de9a741e458196b9600d784b41ad3f942 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 24 Nov 2025 13:48:45 -0500
Subject: [PATCH] StackProtector: Use LibcallLoweringInfo analysis
---
llvm/lib/
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/170329
>From aee9d14de9a741e458196b9600d784b41ad3f942 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 24 Nov 2025 13:48:45 -0500
Subject: [PATCH] StackProtector: Use LibcallLoweringInfo analysis
---
llvm/lib/
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/172796
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/172795
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github-actions[bot] wrote:
# :window: Windows x64 Test Results
* 128788 tests passed
* 2828 tests skipped
* 1 test failed
## Failed Tests
(click on a test name to see its output)
### LLVM
LLVM.Transforms/StackProtector/missing-analysis.ll
```
Exit Code: 1
Command Output (stdout):
--
# RUN:
github-actions[bot] wrote:
# :penguin: Linux x64 Test Results
* 167306 tests passed
* 2957 tests skipped
* 1 test failed
## Failed Tests
(click on a test name to see its output)
### LLVM
LLVM.Transforms/StackProtector/missing-analysis.ll
```
Exit Code: 1
Command Output (stdout):
--
# RUN:
https://github.com/cdevadas edited
https://github.com/llvm/llvm-project/pull/172794
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https://github.com/cdevadas approved this pull request.
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@@ -3587,6 +3587,30 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl,
unsigned BuiltinID,
}
break;
}
+
+ case Builtin::BI__builtin_allow_sanitize_check: {
+Expr *Arg = TheCall->getArg(0);
+// Check if the argument is a string literal.
+const StringL
https://github.com/vitalybuka approved this pull request.
@efriedma-quic do we need some RFC for that?
Similar to
https://discourse.llvm.org/t/rfc-add-llvm-allow-runtime-check-intrinsic/77641
Other than possible redundancy LGTM!
https://github.com/llvm/llvm-project/pull/172030
https://github.com/mshockwave approved this pull request.
LGTM thanks
https://github.com/llvm/llvm-project/pull/172615
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@@ -605,15 +608,117 @@ static Value *emitRsqIEEE1ULP(IRBuilder<> &Builder,
Value *Src,
return Builder.CreateFMul(Rsq, OutputScaleFactor);
}
+/// Emit inverse sqrt expansion for f64 with a correction sequence on top of
+/// v_rsq_f64. This should give a 1ulp result.
+Value *
@@ -9709,6 +9709,30 @@ unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register
SrcReg,
return AMDGPU::COPY;
}
+bool SIInstrInfo::canAddToBBProlog(const MachineInstr &MI) const {
+ uint16_t Opcode = MI.getOpcode();
+ // Check if it is SGPR spill or wwm-register spill Opcode
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