https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/161988
Fix the special case intrinsics that can directly reference a physical
register. There's no reason to use this.
>From e1402218d01f9269d181d69a289e80aa68d84c01 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date:
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
This only matters for subtargets with configurable AGPR allocation.
---
Patch is 159.43 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/161957.diff
25
llvmbot wrote:
@llvm/pr-subscribers-mlir-llvm
@llvm/pr-subscribers-flang-codegen
Author: Sergio Afonso (skatrak)
Changes
This patch introduces the `omp.alloc_shared_mem` and `omp.free_shared_mem`
operations to represent explicit allocations and deallocations of shared memory
across threa
tstellar wrote:
release/20.x branch is frozen now so closing this.
https://github.com/llvm/llvm-project/pull/148643
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https://github.com/tstellar closed
https://github.com/llvm/llvm-project/pull/148643
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https://github.com/bassiounix created
https://github.com/llvm/llvm-project/pull/161993
None
>From 8bf93446dccaff1c82aa9a3a10ca54049176 Mon Sep 17 00:00:00 2001
From: bassiounix
Date: Sun, 5 Oct 2025 06:48:10 +0300
Subject: [PATCH] [libc][math] Refactor exp2f16 implementation to header-only
https://github.com/rampitec approved this pull request.
That's a scalar condition, so really does not depend on wave size. LGTM.
https://github.com/llvm/llvm-project/pull/161801
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ht
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/161762
>From 53a6a5b9e3adcabc51e7eff0a21642f33859b946 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 3 Oct 2025 10:21:10 +0900
Subject: [PATCH] AMDGPU: Remove LDS_DIRECT_CLASS register class
This is a singlet
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/159880
>From 74bae94efb361527a6ad5db59e127014dc0c65c3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 15 Sep 2025 22:41:07 +0900
Subject: [PATCH] TableGen: Support target specialized pseudoinstructions
Allow a
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/159882
>From a8f90376a5de997c3361afe8a87b28a10c6a40a5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 16 Sep 2025 14:54:15 +0900
Subject: [PATCH] CodeGen: Make target overrides of PointerLikeRegClass
mandatory
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/159881
>From 64f0e18b0875e636705e09541ca99c6665ea19b7 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 16 Sep 2025 14:55:52 +0900
Subject: [PATCH] CodeGen: Make all targets override pseudos with pointers
This e
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158278
>From bad7300404b215bc299b68524cd666f6752925c7 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 12 Sep 2025 20:45:56 +0900
Subject: [PATCH] AMDGPU: Stop using aligned VGPR classes for addRegisterClass
Th
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/159885
>From bcaa5f77561898d1c0a83e7be20e5673b0932781 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 17 Sep 2025 21:14:02 +0900
Subject: [PATCH] AMDGPU: Remove wrapper around TRI::getRegClass
This shadows the
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158278
>From bad7300404b215bc299b68524cd666f6752925c7 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 12 Sep 2025 20:45:56 +0900
Subject: [PATCH] AMDGPU: Stop using aligned VGPR classes for addRegisterClass
Th
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