https://github.com/ergawy created
https://github.com/llvm/llvm-project/pull/156610
Extends `do concurrent` to OpenMP device mapping by adding support for mapping
`reduce` specifiers to omp `reduction` clauses. The changes attach 2
`reduction` clauses to the mapped OpenMP construct: one on the
https://github.com/s-barannikov created
https://github.com/llvm/llvm-project/pull/156359
These instructions can now be fully decoded automatically.
>From eb4a0870f4a96eddc73d3ae4aaa9dd987c06b832 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PAT
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From ed2916521d54928b73305de69b1556d1d8a50f5b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From 4188fa46342e6747f985d232677f6a690fa9972c Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From b1cd999acbb29fc53f9eb33284a3e5d2bc72bb11 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155607
>From 20442f6adbd765db0493edabef85228b56b0a1ef Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:35:53 +0900
Subject: [PATCH] AMDGPU: Refactor isImmOperandLegal
The goal is to expose more v
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From 9f30122b180122b518a4dca079145846bb87e428 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/ergawy edited
https://github.com/llvm/llvm-project/pull/155993
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https://github.com/fabianmcg created
https://github.com/llvm/llvm-project/pull/156374
This patch extends `ptr_add` to work with shaped types with value semantics,
both for the offsets and base.
Concretely this patch makes the following changes:
- Supports scalar-to-scalar, scalar-to-shaped, sh
llvmbot wrote:
@llvm/pr-subscribers-mlir-llvm
Author: Fabian Mora (fabianmcg)
Changes
Implements translation from ptr dialect to LLVM IR for core pointer operations:
- `ptr.ptr_add` -> `getelementptr`
- `ptr.load` -> `load` with atomic ordering, volatility, and metadata support
- `ptr.stor
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/156384
Backport 2320529ff77338cd0cb9786b8f195d611edcae77
Requested by: @tangaac
>From f557b56527c19e6209d8bb24a7039a1084822754 Mon Sep 17 00:00:00 2001
From: tangaac
Date: Mon, 1 Sep 2025 18:28:17 +0800
Subject: [PAT
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From 2237e5a7ed147c1a1f279d1549c6e56c24a55d7e Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
s-barannikov wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156361?utm_source=stack-comment-downstack-mergeability-warn
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156402
This was using the legacy multiclass which assumes the base form
has an m0 use. Use the versions which assume no m0 as the base name.
Most of the diff is shuffling around the pattern classes to avoid trying
to mat
cachemeifyoucan wrote:
> This seems good, perhaps after #113363 lands, it'd be interesting to rebase
> and run some build-time tests, just to ensure it doesn't introduce
> regressions.
Yup! We don't see anything on our end but it will be good to double check.
https://github.com/llvm/llvm-proj
https://github.com/tobias-stadler created
https://github.com/llvm/llvm-project/pull/156511
In preparation of larger changes to the bitstream remark format,
refactor the error handling code in the BitstreamRemarkParser.
Main change: move the various static helper methods into the parser
helper c
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 235b15d6a19c5810cdbbb2d111b5f614a86082a0 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155603
>From 5c284f46a1063d5d0788c25a0d37ba019c171d54 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 16:19:23 +0900
Subject: [PATCH 1/2] AMDGPU: Fix fixme for out of bounds indexing in
usesConstan
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154316
>From 34480e096c560bdc47b66febda32a95854ed619a Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Tue, 19 Aug 2025 12:00:53 +
Subject: [PATCH] Identify DeclRefExpr as a use of an origin
---
clang/lib/Analys
llvmbot wrote:
@llvm/pr-subscribers-clangd
Author: Nathan Ridge (HighCommander4)
Changes
Fixes https://github.com/clangd/clangd/issues/2275
---
Full diff: https://github.com/llvm/llvm-project/pull/156284.diff
2 Files Affected:
- (modified) clang-tools-extra/clangd/InlayHints.cpp (+24-7
https://github.com/ergawy edited
https://github.com/llvm/llvm-project/pull/156589
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https://github.com/llvm/llvm-project/pull/147302
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https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 95a0d748eae948d6c520dd4706cac52cc830ecfd Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 6ff221b947f637f100c1e8db3d2df2651beff3af Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
@@ -4447,76 +4447,76 @@
# GFX11: ds_store_b128 v255, v[2:5] offset:65535 ; encoding:
[0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00]
0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00
-# GFX11: ds_store_b16 v0, v1 ; encoding:
[0x00,0x00,0x7c,0xd8,0x00,0x01,0x00,0x00]
+# G
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https://github.com/ergawy edited
https://github.com/llvm/llvm-project/pull/156589
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https://github.com/petrhosek approved this pull request.
https://github.com/llvm/llvm-project/pull/156538
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https://github.com/cmtice approved this pull request.
https://github.com/llvm/llvm-project/pull/156526
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https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From fd7e685e86a7f20048293d8bb9f5a60b613b3737 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
@@ -250,6 +286,9 @@ struct MachineSMEABI : public MachineFunctionPass {
SmallVector BundleStates;
std::optional TPIDR2Block;
std::optional AfterSMEProloguePt;
+Register AgnosticZABufferPtr = AArch64::NoRegister;
+LiveRegs PhysLiveRegsAfterSMEPrologue = LiveR
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From c82858d3ba2267af6638e29d2601715b582a2968 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/156504
Backport 94738ddaf42a0fa1981dc083f9ed94ba11943458
Requested by: @amy-kwan
>From 58a31b4aa15cfa88cade7a0ebe66a14396a7e007 Mon Sep 17 00:00:00 2001
From: David Tenty
Date: Thu, 28 Aug 2025 09:29:27 -0400
Subject
@@ -17,6 +17,46 @@ include "mlir/Interfaces/SideEffectInterfaces.td"
include "mlir/Interfaces/ViewLikeInterface.td"
include "mlir/IR/OpAsmInterface.td"
+//===--===//
+// Common props
+//===
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-vectorizers
Author: None (llvmbot)
Changes
Backport 7730ebce8e8fa84db4da04a7d8fe1977ccbf28ff
Requested by: @nikic
---
Patch is 23.11 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-pr
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From c66fd0b127a34082ebc277ede621073c121ce0dd Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
@@ -633,13 +633,30 @@ class InlayHintVisitor : public
RecursiveASTVisitor {
}
if (auto *AT = D->getType()->getContainedAutoType()) {
- if (AT->isDeduced() && !D->getType()->isDependentType()) {
-// Our current approach is to place the hint on the variable
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154009
>From aa5c2209c8358e5716182e9db2a66a5ddfb4fcfe Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sun, 17 Aug 2025 10:10:18 +
Subject: [PATCH] [LifetimeSafety] Track gsl::Pointer types
---
clang/lib/Analysi
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https://github.com/ergawy created
https://github.com/llvm/llvm-project/pull/156589
Extends support for mapping `do concurrent` on the device by adding support for
`local` specifiers. The changes in this PR map the local variable to the
`omp.target` op and uses the mapped value as the `private`
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From d01399ac76d639e7474a8ae382395d1985e64ff7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From f3b4f276760009154caa8140dc5b92651dfbe4db Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 01a8d9d7026b94f1cf060a8f12ad27df6e70ee2b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156540
>From a4b01316df9cc4cbaddb92c6f62d3803f5b4600d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From ee67c361e4f40b314cd8e2ef4b262f5059c2c40d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156540
>From a4b01316df9cc4cbaddb92c6f62d3803f5b4600d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From ee67c361e4f40b314cd8e2ef4b262f5059c2c40d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 01a8d9d7026b94f1cf060a8f12ad27df6e70ee2b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 1346d77cc53c6a4152eff9a885244daa360254f7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From d01399ac76d639e7474a8ae382395d1985e64ff7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 1346d77cc53c6a4152eff9a885244daa360254f7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From d80acf2607cbe3bdc8beedbad108ddba1f174541 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
@@ -38,11 +38,7 @@ class Enc_041d7b : OpcodeHexagon {
let Inst{7-1} = Ii{8-2};
bits <4> Rs16;
let Inst{19-16} = Rs16{3-0};
- bits <5> n1;
- let Inst{28-28} = n1{4-4};
- let Inst{24-23} = n1{3-2};
- let Inst{13-13} = n1{1-1};
- let Inst{8-8} = n1{0-0};
---
https://github.com/s-barannikov edited
https://github.com/llvm/llvm-project/pull/156361
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https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From d80acf2607cbe3bdc8beedbad108ddba1f174541 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/156764
Backport a862225813c251c28b085603b7d32d4b111dbc57
Requested by: @Michael137
>From 4afd084013a57eb6ae27f46458d9e4115599a6a9 Mon Sep 17 00:00:00 2001
From: Michael Buch
Date: Wed, 3 Sep 2025 20:04:53 +0100
Subje
https://github.com/benshi001 edited
https://github.com/llvm/llvm-project/pull/156361
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156581
>From a09ada3d217bcf5728f32d7a16c334fb0330e617 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 12:06:53 +0900
Subject: [PATCH] AMDGPU: Change FLAT classes to use RegisterOperand parameters
Th
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 25ff1b6a8940230deaa680241f9ce67d7896ab5d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctl
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156655
>From 61b4ecaf9130602ed184ed505be6ed76d7e13f2e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 20:08:48 +0900
Subject: [PATCH] AMDGPU: Fix definitions of DS ret atomics with AGPRs
These are 2
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156696
>From 1b6877bd4a0ef4a30fcd0728b6e1864200969bc8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 00:00:22 +0900
Subject: [PATCH] AMDGPU: Remove the DS special case in getRegClass
These instruct
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156696
>From 1b6877bd4a0ef4a30fcd0728b6e1864200969bc8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 00:00:22 +0900
Subject: [PATCH] AMDGPU: Remove the DS special case in getRegClass
These instruct
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 25ff1b6a8940230deaa680241f9ce67d7896ab5d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctl
https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/156544
>From 02342c922d0feec12b980528eb4a75e8d6676ebe Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Tue, 2 Sep 2025 15:03:11 -0700
Subject: [PATCH 1/3] [HLSL] Use static create methods to initialize individual
reso
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Helena Kotas (hekota)
Changes
Use static methods `__createFromBinding` and `__createFromImplicitBinding` to
initialize individual resources in Sema HLSL. Resources in arrays will be
handles in a separate change.
Depends on #155866
Part
llvmbot wrote:
@llvm/pr-subscribers-hlsl
Author: Helena Kotas (hekota)
Changes
Use static methods `__createFromBinding` and `__createFromImplicitBinding` to
initialize individual resources in Sema HLSL. Resources in arrays will be
handles in a separate change.
Depends on #155866
Part 2
cachemeifyoucan wrote:
Before landing the other change and rebase this, I created a branch to
benchmark compile time:
https://llvm-compile-time-tracker.com/compare.php?from=3b3fc701d8f83d4ca30ee1c818fb7687336ac178&to=e5febfb1d9d880b4f7af5dc32194f479ee2adcd6&stat=instructions%3Au
Nothing stands
cjappl wrote:
Sounds good, and totally understood. Thanks for helping us understand the
general process and precedent @tru
We have reached out to the original bug reporter and are going to ask if some
proposed workarounds will service until LLVM 22. I will ping you on here when I
have an ide
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 22f1911b5b5f7a25d5d9cb74feb864341ef9a782 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctl
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156696
>From c7238cff2feb2f7e1e7d7b0f55ae5b9917a682a2 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 00:00:22 +0900
Subject: [PATCH] AMDGPU: Remove the DS special case in getRegClass
These instruct
github-actions[bot] wrote:
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This PR will be automatically labeled and the relevant teams will be notified.
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https://github.com/hekota ready_for_review
https://github.com/llvm/llvm-project/pull/156544
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 22f1911b5b5f7a25d5d9cb74feb864341ef9a782 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctl
tru wrote:
Are we happy / confident with this one now? @philnik777 @ldionne ?
https://github.com/llvm/llvm-project/pull/155712
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https://github.com/llvm/llvm-project/pull/156363
>From f3b4f276760009154caa8140dc5b92651dfbe4db Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
@@ -0,0 +1,334 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
arsenm wrote:
No. This needs new support in AMDGPURewriteAGPRCopyMFMA (which will also need a
renaming...)
https://github.com/llvm/llvm-proje
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
benshi001 wrote:
https://github.com/hekota converted_to_draft
https://github.com/llvm/llvm-project/pull/156544
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Author: Sjoerd Meijer
Date: 2025-09-03T20:00:34+01:00
New Revision: bbbe5384f1f231d7e206a37d43f30dc3b4975f96
URL:
https://github.com/llvm/llvm-project/commit/bbbe5384f1f231d7e206a37d43f30dc3b4975f96
DIFF:
https://github.com/llvm/llvm-project/commit/bbbe5384f1f231d7e206a37d43f30dc3b4975f96.diff
davemgreen wrote:
I managed to reproduce the original error and check that this fixes it. The
extra EH_LABELS that needed to be removed were added in b933f0c376c9.
https://github.com/llvm/llvm-project/pull/156170
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l
https://github.com/davemgreen approved this pull request.
https://github.com/llvm/llvm-project/pull/156170
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https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133531
>From 96e7da9a083888683c2ba00d97f886fd748ea10b Mon Sep 17 00:00:00 2001
From: Peter Collingbourne
Date: Wed, 9 Apr 2025 20:30:57 -0700
Subject: [PATCH 1/2] Undo unnecessary change
Created using spr 1.3.6-beta.1
---
https://github.com/HighCommander4 updated
https://github.com/llvm/llvm-project/pull/156284
>From 6791b7af77579242a7a0dd6a35929c0a648835d0 Mon Sep 17 00:00:00 2001
From: Nathan Ridge
Date: Mon, 1 Sep 2025 02:48:44 -0400
Subject: [PATCH] [clangd] Show type hint for simple cases of dependent 'auto
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156406?utm_source=stack-comment-downstack-mergeability-warning";
DavidSpickett wrote:
Actually the problem is that there is a pipeline wide timeout of 2 hours. This
is reasonable most of the time but sometimes our AArch64 builds are taking >
2h. I will address this on our side.
Could that be due to a test taking ages, maybe, but probably not given we've
ha
https://github.com/MacDue created
https://github.com/llvm/llvm-project/pull/156674
None
>From c36bbc21aa552fb3c4c63df76df5f5de3610c46b Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell
Date: Tue, 2 Sep 2025 17:14:25 +
Subject: [PATCH] [WIP] Refactor MachineSMEABIPass state
Change-Id: I3ec3d
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp --
clang/lib/Analysis/LifetimeSafety.cpp
clang/test/Sem
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154316
>From 613942a19bbde5b905adb9552fa7dc106f76152c Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Tue, 19 Aug 2025 12:00:53 +
Subject: [PATCH] Identify DeclRefExpr as a use of an origin
---
clang/lib/Analys
@@ -271,35 +276,51 @@ static void ConnectEpilog(Loop *L, Value *ModVal,
BasicBlock *NewExit,
NewExit);
// Now PHIs should look like:
// NewExit:
-// PN = PHI [I, Latch], [poison, PreHeader]
+// PN = PHI [I, Latch]
// ...
@@ -250,6 +286,9 @@ struct MachineSMEABI : public MachineFunctionPass {
SmallVector BundleStates;
MacDue wrote:
Here's a WIP patch that implements the scheme I mentioned previously:
https://github.com/llvm/llvm-project/pull/156674
https://github.com/llvm/
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154316
>From fffc8d6575370ff5f59379dca01b2c1396b52c50 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Tue, 19 Aug 2025 12:00:53 +
Subject: [PATCH] Identify DeclRefExpr as a use of an origin
---
clang/lib/Analys
https://github.com/mtrofin approved this pull request.
https://github.com/llvm/llvm-project/pull/156549
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https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154009
>From ab16e9aa72482026ed1ca48cd9e245fd4eaade9a Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sun, 17 Aug 2025 10:10:18 +
Subject: [PATCH] [LifetimeSafety] Track gsl::Pointer types
---
clang/lib/Analysi
@@ -271,35 +276,51 @@ static void ConnectEpilog(Loop *L, Value *ModVal,
BasicBlock *NewExit,
NewExit);
// Now PHIs should look like:
// NewExit:
-// PN = PHI [I, Latch], [poison, PreHeader]
+// PN = PHI [I, Latch]
// ...
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/154009
>From 447c9ba2cc7d4a886a3c5c40d54bb1b3bcab2255 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sun, 17 Aug 2025 10:10:18 +
Subject: [PATCH] [LifetimeSafety] Track gsl::Pointer types
---
clang/lib/Analysi
@@ -23,6 +24,41 @@ class LLVM_Attrhttps://github.com/llvm/llvm-project/pull/156374
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@@ -23,6 +24,41 @@ class LLVM_Attrhttps://github.com/llvm/llvm-project/pull/156374
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@@ -23,6 +24,41 @@ class LLVM_Attrhttps://github.com/llvm/llvm-project/pull/156374
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llvmbot wrote:
@llvm/pr-subscribers-lld-macho
Author: Aiden Grossman (boomanaiden154)
Changes
Subshells are not supported in the lit internal shell. We can remove
them by constructing sed commands directly inside of a separate file.
Towards #102700.
---
Full diff: https://github.com/llv
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