@@ -864,6 +864,16 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
return TyBits - 1; // Every always-zero bit is a sign bit.
break;
}
+ case TargetOpcode::G_ASHR: {
+Register Src1 = MI.getOperand(1).getReg();
+Register Src2 = MI.getOperand(2)
@@ -279,6 +278,7 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
#ifndef DUMMY_FUNCTION_PASS
#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME)
#endif
+DUMMY_FUNCTION_PASS("tlshoist", TLSVariableHoistPass)
optimisan wrote:
I'll remove this list entirely since it's the same in
https://github.com/davemgreen approved this pull request.
https://github.com/llvm/llvm-project/pull/139222
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davemgreen wrote:
LGTM - changes look small and correct a regression since the previous release.
https://github.com/llvm/llvm-project/pull/139222
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https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
>From 5e50922e53ad2de7e3c68242ad78f1813a48f7b6 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa
---
llvm/lib/Target/RI
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
>From 5e50922e53ad2de7e3c68242ad78f1813a48f7b6 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa
---
llvm/lib/Target/RI
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 7fdbd6b564697b7f0fd7ffd1f031671c3036 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
ex
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 7fdbd6b564697b7f0fd7ffd1f031671c3036 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
ex
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
>From 6dc27676de2a685404abd0cfd12cff95703a1cf1 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa
---
llvm/lib/Target/RI
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 9205ac04544703aaee2a1475763ce7bc7495ccab Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
ex
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
>From 6dc27676de2a685404abd0cfd12cff95703a1cf1 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa
---
llvm/lib/Target/RI
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 9205ac04544703aaee2a1475763ce7bc7495ccab Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
ex
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138495
>From 476894ffa1fed64724b91c8b1db9391e09295be6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:47:42 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port InitUndef to NPM
---
llvm/include/llvm/C
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138829
>From dbd76c614cb19179ffc0a20a19341a7e58a1431b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 14:12:36 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port ProcessImplicitDefs to NPM
---
llvm/incl
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138828
>From a9bab6452880f4200f4ce2d8c938eacd68d6bbc7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 11:04:05 +
Subject: [PATCH 1/2] [CodeGen][NPM] Register Function Passes
---
llvm/include/llv
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138491
>From dc9a3165d3625002d2122dfd0e1dbe262a399e74 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 06:30:03 +
Subject: [PATCH] [AMDGPU][NPM] Complete optimized regalloc pipeline
Also fill in s
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138670
>From ea3103a3be32909978894364c1b481cb80c2fc67 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:55:07 +
Subject: [PATCH] [CodeGen][NPM] Read TargetMachine's EnableIPRA option
---
llvm/i
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138670
>From ea3103a3be32909978894364c1b481cb80c2fc67 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:55:07 +
Subject: [PATCH] [CodeGen][NPM] Read TargetMachine's EnableIPRA option
---
llvm/i
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138830
>From 67f7f32e9ca0a8befc28b7504e9e7f141d771eae Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 7 May 2025 08:57:31 +
Subject: [PATCH] [CodeGen][NPM] Account inserted passes for -start/stop
options
-
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138660
>From 838e904009527297d38e79572745a810cfa34d60 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:05:52 +
Subject: [PATCH] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138496
>From ff19035e9f213592109e7ee2c4fb2b667ba9a333 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:58:58 +
Subject: [PATCH] [AMDGPU][NPM] Register AMDGPUWaitSGPRHazards pass
---
llvm/lib/T
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138495
>From 476894ffa1fed64724b91c8b1db9391e09295be6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:47:42 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port InitUndef to NPM
---
llvm/include/llvm/C
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138828
>From a9bab6452880f4200f4ce2d8c938eacd68d6bbc7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 11:04:05 +
Subject: [PATCH 1/2] [CodeGen][NPM] Register Function Passes
---
llvm/include/llv
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138491
>From dc9a3165d3625002d2122dfd0e1dbe262a399e74 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 06:30:03 +
Subject: [PATCH] [AMDGPU][NPM] Complete optimized regalloc pipeline
Also fill in s
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138496
>From ff19035e9f213592109e7ee2c4fb2b667ba9a333 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:58:58 +
Subject: [PATCH] [AMDGPU][NPM] Register AMDGPUWaitSGPRHazards pass
---
llvm/lib/T
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138497
>From 41492e43dad53cefb3ee220a13e75f062351c1cc Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 09:17:40 +
Subject: [PATCH] [CodeGen][NPM] Port PostRAMachineSinking to NPM
---
llvm/include
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138660
>From 838e904009527297d38e79572745a810cfa34d60 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:05:52 +
Subject: [PATCH] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138830
>From 67f7f32e9ca0a8befc28b7504e9e7f141d771eae Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 7 May 2025 08:57:31 +
Subject: [PATCH] [CodeGen][NPM] Account inserted passes for -start/stop
options
-
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/139516
None
Rate limit · GitHub
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https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/139517
This replaces the Invalidate pass.
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optimisan wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/139516?utm_source=stack-comment-downstack-mergeability-warning
optimisan wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/139517?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/138670
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Akshat Oke (optimisan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/139516.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+6)
- (modified) llvm/lib/Target/AMDGPU/AMDGPU
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/139517
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https://github.com/optimisan edited
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Akshat Oke (optimisan)
Changes
This replaces the Invalidate pass.
There are no cross-function analysis requirements right now, so clearing all
analyses works for the last pass in the pipeline.
---
Havi
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/139517
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https://github.com/llvm/llvm-project/pull/139517
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/139517
>From ae761dee3ece71d4813b62a2600cf4565b893239 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 12 May 2025 08:02:22 +
Subject: [PATCH 1/2] [CodeGen][NPM] Introduce FreeAllAnalysesPass
This replaces t
https://github.com/el-ev created
https://github.com/llvm/llvm-project/pull/139508
None
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el-ev wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/139508?utm_source=stack-comment-downstack-mergeability-warning";
>
https://github.com/el-ev ready_for_review
https://github.com/llvm/llvm-project/pull/139508
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llvmbot wrote:
@llvm/pr-subscribers-mc
Author: Iris Shi (el-ev)
Changes
---
Patch is 25.59 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/139508.diff
5 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td (+29)
- (added
https://github.com/jayfoad requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/139503
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@@ -864,6 +864,16 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
return TyBits - 1; // Every always-zero bit is a sign bit.
break;
}
+ case TargetOpcode::G_ASHR: {
+Register Src1 = MI.getOperand(1).getReg();
+Register Src2 = MI.getOperand(2)
https://github.com/el-ev edited https://github.com/llvm/llvm-project/pull/139508
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@@ -2432,12 +2437,40 @@ static void
tryToCreateAbstractReductionRecipe(VPReductionRecipe *Red,
Red->replaceAllUsesWith(AbstractR);
}
+/// This function tries to create an abstract recipe from a partial reduction
to
+/// hide its mul and extends from cost estimation.
+stati
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 02b755091def57f5cf541ed04b7a0b8283ba267d Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
ex
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
>From 6f4a034604e939cad0fa25c0b11768667c213ec6 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa
---
llvm/lib/Target/RI
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 02b755091def57f5cf541ed04b7a0b8283ba267d Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
ex
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
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https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
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@@ -1842,23 +1859,52 @@ CharLiteralParser::CharLiteralParser(const char *begin,
const char *end,
HadError = true;
PP.Diag(Loc, diag::err_character_too_large);
}
+ if (!HadError && Converter) {
+assert(Kind != tok::wide_cha
@@ -1842,23 +1859,52 @@ CharLiteralParser::CharLiteralParser(const char *begin,
const char *end,
HadError = true;
PP.Diag(Loc, diag::err_character_too_large);
}
+ if (!HadError && Converter) {
+assert(Kind != tok::wide_cha
@@ -146,6 +144,8 @@ static unsigned ProcessCharEscape(const char *ThisTokBegin,
// that would have been \", which would not have been the end of string.
unsigned ResultChar = *ThisTokBuf++;
char Escape = ResultChar;
+ bool Translate = true;
cor3ntin wrot
@@ -416,8 +416,7 @@ Builtin Macros
``__clang_literal_encoding__``
Defined to a narrow string literal that represents the current encoding of
narrow string literals, e.g., ``"hello"``. This macro typically expands to
- "UTF-8" (but may change in the future if the
- ``-fexe
@@ -246,18 +249,19 @@ class StringLiteralParser {
StringLiteralEvalMethod EvalMethod;
public:
- StringLiteralParser(ArrayRef StringToks, Preprocessor &PP,
- StringLiteralEvalMethod StringMethod =
- StringLiteralEvalMethod::Evalu
@@ -0,0 +1,36 @@
+//===--- clang/Lex/LiteralConverter.h - Translator for Literals -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,36 @@
+//===--- clang/Lex/LiteralConverter.h - Translator for Literals -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -491,6 +491,9 @@ class Triple {
/// For example, "fooos1.2.3" would return "1.2.3".
StringRef getEnvironmentVersionString() const;
+ /// getSystemCharset - Get the system charset of the triple.
+ StringRef getSystemCharset() const;
+
cor3ntin wrote:
@@ -367,6 +370,15 @@ static unsigned ProcessCharEscape(const char *ThisTokBegin,
HadError = true;
}
+ if (Translate && Converter) {
+// Invalid escapes are written as '?' and then translated.
+char ByteChar = Invalid ? '?' : ResultChar;
+SmallString<8> Resul
@@ -0,0 +1,36 @@
+//===--- clang/Lex/LiteralConverter.h - Translator for Literals -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -633,6 +633,9 @@ class LangOptions : public LangOptionsBase {
bool AtomicFineGrainedMemory = false;
bool AtomicIgnoreDenormalMode = false;
+ /// Name of the exec charset to convert the internal charset to.
+ std::string ExecCharset;
cor3ntin wrote:
L
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
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https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
>From 537ccab69c5d426109d9c9948f55c532e83b0ecf Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa
---
llvm/lib/Target/RI
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 5c454f3091822039e98bcff0693db1e7a5205351 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
ex
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/139516
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@@ -1200,6 +1200,13 @@ def : Pat<(i16 (atomic_load_nonext_16 addr:$src)),
(MOV16rm addr:$src)>;
def : Pat<(i32 (atomic_load_nonext_32 addr:$src)), (MOV32rm addr:$src)>;
def : Pat<(i64 (atomic_load_nonext_64 addr:$src)), (MOV64rm addr:$src)>;
+def : Pat<(v4i32 (scalar_to_vecto
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/139531
By the pseudocode in the ISA manual, if any input is a nan it acts
like min3, which will fold to min2 of the other operands. The other
cases fold to min, I'm not sure how this one was wrong.
>From 069254f8608ac85
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/139530
None
>From 012d451378314c9633c3a38891fca23c027e54b5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 12 May 2025 10:42:16 +0200
Subject: [PATCH] AMDGPU: Disable most fmed3 folds for strictfp
---
.../li
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/139530
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
By the pseudocode in the ISA manual, if any input is a nan it acts
like min3, which will fold to min2 of the other operands. The other
cases fold to min, I'm not sure how this one was wrong.
---
Ful
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/139531
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/139530?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/jroelofs approved this pull request.
https://github.com/llvm/llvm-project/pull/138696
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https://github.com/joaosaffran edited
https://github.com/llvm/llvm-project/pull/138318
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@@ -0,0 +1,200 @@
+// RUN: %clang_analyze_cc1 -analyzer-checker=core,debug.ExprInspection
-verify=expected,default %s
+// RUN: %clang_analyze_cc1 -analyzer-checker=core,debug.ExprInspection
-analyzer-config inline-functions-with-ambiguous-loops=true
-verify=expected,enabled %s
https://github.com/NagyDonat commented:
I read this rebased code and IMO it should work -- however I found a whitespace
error that originated in my commit :sweat_smile:
https://github.com/llvm/llvm-project/pull/139597
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https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/139508
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https://github.com/NagyDonat edited
https://github.com/llvm/llvm-project/pull/139597
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arsenm wrote:
### Merge activity
* **May 12, 2:11 PM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/139531).
https://github.com/llvm/llvm-project/pull/139531
_
arsenm wrote:
### Merge activity
* **May 12, 2:11 PM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/139530).
https://github.com/llvm/llvm-project/pull/139530
_
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Alexander Richardson (arichardson)
Changes
While we can only reason about the index/address, the G_PTRTOINT
operations returns all representation bits, so we can't assume the
remaining ones are all zeroes.
This behaviour was clarif
https://github.com/arichardson created
https://github.com/llvm/llvm-project/pull/139608
While we can only reason about the index/address, the G_PTRTOINT
operations returns all representation bits, so we can't assume the
remaining ones are all zeroes.
This behaviour was clarified as part of the d
arichardson wrote:
Now that we use the full bitwidth the high KnownBits are no longer zext'ed to
zeroes. But maybe the better approahc would be to just do KnownBits on the
address bits and set the high bits to unknown?
That should fix the issue as well?
https://github.com/llvm/llvm-project/pu
llvmbot wrote:
@llvm/pr-subscribers-clang-static-analyzer-1
Author: Balazs Benics (steakhal)
Changes
Recently some users reported that they observed large increases of runtime (up
to +600% on some translation units) when they upgraded to a more recent
(slightly patched, internal) clang v
https://github.com/steakhal milestoned
https://github.com/llvm/llvm-project/pull/139597
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https://github.com/steakhal created
https://github.com/llvm/llvm-project/pull/139597
Recently some users reported that they observed large increases of runtime (up
to +600% on some translation units) when they upgraded to a more recent
(slightly patched, internal) clang version. Bisection reve
llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
Author: Alexander Richardson (arichardson)
Changes
We lower ptrtoaddr by emitting a G_PTRTOINT, truncating that to the
address size and then truncate/zext to the final integer type.
This has exposed an issue in the GlobalIsel postlegaliz
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Alexander Richardson (arichardson)
Changes
We lower ptrtoaddr by emitting a G_PTRTOINT, truncating that to the
address size and then truncate/zext to the final integer type.
This has exposed an issue in the GlobalIsel postlegalize
@@ -1952,6 +1953,22 @@ PtrParts SplitPtrStructs::visitPtrToIntInst(PtrToIntInst
&PI) {
return {nullptr, nullptr};
}
+PtrParts SplitPtrStructs::visitPtrToAddrInst(PtrToAddrInst &PA) {
+ Value *Ptr = PA.getPointerOperand();
+ if (!isSplitFatPtr(Ptr->getType()))
+return
https://github.com/krzysz00 edited
https://github.com/llvm/llvm-project/pull/139413
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https://github.com/krzysz00 approved this pull request.
One tiny nit, lgtm otherwise
https://github.com/llvm/llvm-project/pull/139413
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https://github.com/arichardson created
https://github.com/llvm/llvm-project/pull/139601
We lower ptrtoaddr by emitting a G_PTRTOINT, truncating that to the
address size and then truncate/zext to the final integer type.
This has exposed an issue in the GlobalIsel postlegalizer combines where
the
@@ -5773,7 +5773,7 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL,
StringRef TT) {
if (!DL.contains("-p7") && !DL.starts_with("p7"))
Res.append("-p7:160:256:256:32");
if (!DL.contains("-p8") && !DL.starts_with("p8"))
- Res.append("-p8:128:128");
+
https://github.com/vitalybuka approved this pull request.
https://github.com/llvm/llvm-project/pull/139389
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https://github.com/arichardson updated
https://github.com/llvm/llvm-project/pull/139357
>From 25dc175562349410f161ef0e80246301d9a7ba79 Mon Sep 17 00:00:00 2001
From: Alex Richardson
Date: Fri, 9 May 2025 22:43:37 -0700
Subject: [PATCH] fix docs build
Created using spr 1.3.6-beta.1
---
llvm/do
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