[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scale_fp4<->f32 for gfx950 (PR #117743)

@@ -14,8 +14,6 @@ typedef __bf16 __attribute__((ext_vector_type(2))) bfloat2; typedef float __attribute__((ext_vector_type(16))) float16; typedef half __attribute__((ext_vector_type(2))) half2; typedef float __attribute__((ext_vector_type(2))) float2; -typedef half __attribute_

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & codegen support for v_cvt_scalef32_pk32_{bf|f}16_{bf|fp}6 for gfx950 (PR #117747)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117747 >From de06178fb74651102c5d6907946a9427812ead77 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Mon, 22 Apr 2024 05:29:12 -0400 Subject: [PATCH] AMDGPU: Builtin & codegen support for v_cvt_scalef32_pk32_{bf|f}

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scale_fp4<->f32 for gfx950 (PR #117743)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117743 >From a4863f1ff55c792b29151b7b86a1b0ff2d16224c Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 19 Apr 2024 11:21:32 -0400 Subject: [PATCH] AMDGPU: Builtins & Codegen support for v_cvt_scale_fp4<->f32 for

[llvm-branch-commits] [clang] [llvm] Builtins & Codegen support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 for gfx950 (PR #117742)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117742 >From da6bd3646c2f839445e612aef6fe0bceeeac9c89 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 19 Apr 2024 03:09:43 -0400 Subject: [PATCH] Builtins & Codegen support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{f|bf}16_fp4 for gfx950 (PR #117744)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117744 >From 8241bf97f4db47adf6116f238159b2831a6266a8 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Mon, 22 Apr 2024 01:58:18 -0400 Subject: [PATCH] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{f|bf}1

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (PR #117793)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117793 OPSEL[0] selects src_word to read. Co-authored-by: Pravin Jagtap >From cf19702d65660fe54b889fcb47091773a19a3e72 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Tue, 23 Apr 2024 03:41:27 -0400 Subject: [PATC

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk32_f32_[fp|bf]6 for gfx950 (PR #117745)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117745 >From 5cf4b44b510ef71aeaa0a7ae3865af290333a3bd Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Mon, 22 Apr 2024 04:45:35 -0400 Subject: [PATCH] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk32_f32_[f

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (PR #117796)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117796 Co-authored-by: Shilei Tian >From d880fd934319fa019b4a8826d383a5809bf2ae0c Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Mon, 3 Jun 2024 16:40:22 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_sr_{f16|b

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117797)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117797 Co-authored-by: Shilei Tian >From 9c5b5a842d40c9a845c97c91e62b9e2d1f613690 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 4 Jun 2024 09:16:19 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (PR #117794)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117794 These instructions have non-standard use of OPSEL bits to select dest write byte. The src2_modifiers operand is used without having its corresponding src2 operand by introducing dummy src2. OPSEL ASM OPSEL Syntax

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (PR #117798)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117798 Co-authored-by: Shilei Tian >From d1793ac38a5b0a9410c99aaae7e87d4f1d020578 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Mon, 3 Jun 2024 09:44:01 -0400 Subject: [PATCH] AMDGPU: Builtin & CodeGen support for

[llvm-branch-commits] [llvm] AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (PR #117795)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117795 Co-authored-by: Shilei Tian >From 50432fb64690cd96b52b75abcfd8967a7e45dc4f Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Fri, 31 May 2024 14:07:52 -0400 Subject: [PATCH] AMDGPU: MC support for V_CVT_SCALE_SR

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (PR #117794)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117794?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (PR #117796)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117796?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (PR #117793)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117793 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (PR #117794)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117794 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (PR #117796)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (PR #117795)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117795 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (PR #117795)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117795 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (PR #117793)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117793 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (PR #117794)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117794 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (PR #117796)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (PR #117798)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117798 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (PR #117798)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117798 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117797)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117797 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117797)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117797 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libc] 590814b - Revert "[libc] Implement process_mrelease. (#117503)"

Author: lntue Date: 2024-11-26T18:02:08-05:00 New Revision: 590814b3d773187ca1fec7de170bde470a00a875 URL: https://github.com/llvm/llvm-project/commit/590814b3d773187ca1fec7de170bde470a00a875 DIFF: https://github.com/llvm/llvm-project/commit/590814b3d773187ca1fec7de170bde470a00a875.diff LOG: Re

[llvm-branch-commits] [compiler-rt] [TySan] Fix struct access with different bases (PR #108385)

https://github.com/gbMattN updated https://github.com/llvm/llvm-project/pull/108385 >From 4f5a7f198988a45fe64b9d1ba88e68a6d7f14e32 Mon Sep 17 00:00:00 2001 From: Matthew Nagy Date: Thu, 12 Sep 2024 12:36:57 + Subject: [PATCH 1/3] [TySan] Fix struct access with different bases --- compiler

[llvm-branch-commits] [llvm] AMDGPU: Make v2f16 minimum/maximum legal for gfx950 (PR #117738)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes --- Patch is 186.69 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/117738.diff 6 Files Affected: - (modified) llvm/lib/Target/AMDGPU/SIISelLowering.

[llvm-branch-commits] [flang] [MLIR][OpenMP] Add Lowering support for OpenMP Declare Mapper directive (PR #117046)

@@ -2701,7 +2701,42 @@ static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, semantics::SemanticsContext &semaCtx, lower::pft::Evaluation &eval, const parser::OpenMPDeclareMapperConstruct &declareMapperConstruct) { - TODO(converter.getC

[llvm-branch-commits] [clang] [PAC][clang] Add new features to pauthtest ABI (PR #113150)

kovdan01 wrote: @MaskRay Would be glad to see your feedback on the changes https://github.com/llvm/llvm-project/pull/113150 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bra

[llvm-branch-commits] [clang] [PAC][clang] Handle pauthtest environment and ABI in Linux-specific code (PR #113151)

kovdan01 wrote: @MaskRay Would be glad to see your feedback on the changes https://github.com/llvm/llvm-project/pull/113151 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bra

[llvm-branch-commits] [compiler-rt] [TySan] Fix struct access with different bases (PR #108385)

https://github.com/gbMattN updated https://github.com/llvm/llvm-project/pull/108385 >From 4f5a7f198988a45fe64b9d1ba88e68a6d7f14e32 Mon Sep 17 00:00:00 2001 From: Matthew Nagy Date: Thu, 12 Sep 2024 12:36:57 + Subject: [PATCH 1/2] [TySan] Fix struct access with different bases --- compiler

[llvm-branch-commits] [compiler-rt] [TySan] Fix struct access with different bases (PR #108385)

github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff 8e6e62d0dee48a696afd0c7d53d74eaccef97b5e 6f795458c4c16522533dbdcb4d8ace299bfda9ff --e

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{f|bf}16_fp4 for gfx950 (PR #117744)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117744 >From b5c2479e4d0e87b5a866b783b70cf371c3b94aff Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Mon, 22 Apr 2024 01:58:18 -0400 Subject: [PATCH] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{f|bf}1

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk32_f32_[fp|bf]6 for gfx950 (PR #117745)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117745 >From c28a3f327ee110db85b7aaf1e12951b92a53e0eb Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Mon, 22 Apr 2024 04:45:35 -0400 Subject: [PATCH] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk32_f32_[f

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & codegen support for v_cvt_scalef32_pk32_{bf|f}16_{bf|fp}6 for gfx950 (PR #117747)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117747 >From 13b0656d2ec90c4a0347cdd65e86af0fb7b1b2c4 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Mon, 22 Apr 2024 05:29:12 -0400 Subject: [PATCH] AMDGPU: Builtin & codegen support for v_cvt_scalef32_pk32_{bf|f}

[llvm-branch-commits] [clang] [llvm] Builtins & Codegen support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 for gfx950 (PR #117742)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117742 >From 1f5f6cfc78b4043086427bb73a9c72c1ae2435de Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 19 Apr 2024 03:09:43 -0400 Subject: [PATCH] Builtins & Codegen support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}

[llvm-branch-commits] [llvm] AMDGPU: Make v2f16 minimum/maximum legal for gfx950 (PR #117738)

arsenm wrote: ### Merge activity * **Nov 26, 2:41 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117738). https://github.com/llvm/llvm-project/pull/117738 _

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_{fp8|bf8}_f32 for gfx950 (PR #117740)

arsenm wrote: ### Merge activity * **Nov 26, 2:41 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117740). https://github.com/llvm/llvm-project/pull/117740 _

[llvm-branch-commits] [llvm] AMDGPU: Handle f32 minimum3/maximum3 pattern for gfx950 (PR #117737)

arsenm wrote: ### Merge activity * **Nov 26, 2:41 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117737). https://github.com/llvm/llvm-project/pull/117737 _

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for: v_cvt_scalef32_[f16|f32]_[bf8|fp8] (PR #117739)

arsenm wrote: ### Merge activity * **Nov 26, 2:41 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117739). https://github.com/llvm/llvm-project/pull/117739 _

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (PR #117794)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117794 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (PR #117794)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes These instructions have non-standard use of OPSEL bits to select dest write byte. The src2_modifiers operand is used without having its corresponding src2 operand by introducing dummy src2. OPSEL AS

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (PR #117796)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (PR #117796)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Shilei Tian --- Full diff: https://github.com/llvm/llvm-project/pull/117796.diff 7 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+10) - (mo

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scale_fp4<->f32 for gfx950 (PR #117743)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117743 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (PR #117795)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117795 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (PR #117795)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Shilei Tian --- Full diff: https://github.com/llvm/llvm-project/pull/117795.diff 5 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmPar

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (PR #117798)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117798 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (PR #117798)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Shilei Tian --- Patch is 32.71 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/117798.diff 8 Files Affected: - (

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117797)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Shilei Tian --- Full diff: https://github.com/llvm/llvm-project/pull/117797.diff 5 Files Affected: - (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.td (+3) -

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117797)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117797 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_{fp8|bf8}_f32 for gfx950 (PR #117740)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117740 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (PR #117798)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117798?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117797)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117797?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (PR #117793)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117793?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (PR #117795)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117795?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (PR #117793)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes OPSEL[0] selects src_word to read. Co-authored-by: Pravin Jagtap --- Patch is 22.27 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/p

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (PR #117793)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117793 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (PR #117793)

llvmbot wrote: @llvm/pr-subscribers-clang Author: Matt Arsenault (arsenm) Changes OPSEL[0] selects src_word to read. Co-authored-by: Pravin Jagtap --- Patch is 22.27 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/11779

[llvm-branch-commits] [flang] [flang][OpenMP] Rename some `Type` members in OpenMP clauses (PR #117784)

https://github.com/kparzysz updated https://github.com/llvm/llvm-project/pull/117784 >From ee00ecdc5a8b342c80ef34a8e1a1c8bb91855ab8 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 26 Nov 2024 09:01:49 -0600 Subject: [PATCH 1/2] [flang][OpenMP] Rename some `Type` members in OpenMP

[llvm-branch-commits] [flang] [flang][OpenMP] Use new modifiers with AFFINITY/ALIGNED/DEVICE (PR #117786)

https://github.com/kparzysz updated https://github.com/llvm/llvm-project/pull/117786 >From 09b1270faf2dc5125c36c7f4cc246b3a922d5b08 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Mon, 25 Nov 2024 14:55:37 -0600 Subject: [PATCH 1/2] [flang][OpenMP] Use new modifiers with AFFINITY/ALIG

[llvm-branch-commits] [clang] 638427b - Revert "[NFC][clang] Add ubsan-trap-merge.c test to show absence of nomerge (…"

Author: Thurston Dang Date: 2024-11-26T14:27:18-08:00 New Revision: 638427b08f7308f388b7f0bdaf426ca1f58e1b18 URL: https://github.com/llvm/llvm-project/commit/638427b08f7308f388b7f0bdaf426ca1f58e1b18 DIFF: https://github.com/llvm/llvm-project/commit/638427b08f7308f388b7f0bdaf426ca1f58e1b18.diff

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scale_fp4<->f32 for gfx950 (PR #117743)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117743 >From 5546fca6e9dffc07b215fcd6752f34ff99554c8b Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 19 Apr 2024 11:21:32 -0400 Subject: [PATCH] AMDGPU: Builtins & Codegen support for v_cvt_scale_fp4<->f32 for

[llvm-branch-commits] [flang] [flang][OpenMP] Rename some `Type` members in OpenMP clauses (PR #117784)

llvmbot wrote: @llvm/pr-subscribers-flang-openmp Author: Krzysztof Parzyszek (kparzysz) Changes The intent is to keep names in sync with the terminology from the OpenMP spec: ``` OmpBindClause::Type -> Binding OmpDefaultClause::Type-> DataSharingAttribute OmpDeviceTypeClaus

[llvm-branch-commits] [flang] [flang][OpenMP] Rename some `Type` members in OpenMP clauses (PR #117784)

llvmbot wrote: @llvm/pr-subscribers-flang-parser Author: Krzysztof Parzyszek (kparzysz) Changes The intent is to keep names in sync with the terminology from the OpenMP spec: ``` OmpBindClause::Type -> Binding OmpDefaultClause::Type-> DataSharingAttribute OmpDeviceTypeClaus

[llvm-branch-commits] [flang] [flang][OpenMP] Rename some `Type` members in OpenMP clauses (PR #117784)

llvmbot wrote: @llvm/pr-subscribers-flang-semantics Author: Krzysztof Parzyszek (kparzysz) Changes The intent is to keep names in sync with the terminology from the OpenMP spec: ``` OmpBindClause::Type -> Binding OmpDefaultClause::Type-> DataSharingAttribute OmpDeviceTypeCl

[llvm-branch-commits] [flang] [flang][OpenMP] Rename some `Type` members in OpenMP clauses (PR #117784)

https://github.com/kparzysz created https://github.com/llvm/llvm-project/pull/117784 The intent is to keep names in sync with the terminology from the OpenMP spec: ``` OmpBindClause::Type -> Binding OmpDefaultClause::Type-> DataSharingAttribute OmpDeviceTypeClause::Type -> Device

[llvm-branch-commits] [flang] [flang][OpenMP] Use new modifiers with AFFINITY/ALIGNED/DEVICE (PR #117786)

https://github.com/kparzysz created https://github.com/llvm/llvm-project/pull/117786 This is a mostly mechanical change from specific modifiers embedded directly in a clause to the Modifier variant. Additional comments and references to the OpenMP specs were added. >From 09b1270faf2dc5125c36c

[llvm-branch-commits] [flang] [flang][OpenMP] Use new modifiers with AFFINITY/ALIGNED/DEVICE (PR #117786)

llvmbot wrote: @llvm/pr-subscribers-flang-openmp Author: Krzysztof Parzyszek (kparzysz) Changes This is a mostly mechanical change from specific modifiers embedded directly in a clause to the Modifier variant. Additional comments and references to the OpenMP specs were added. --- Patch

[llvm-branch-commits] [flang] [flang][OpenMP] Use new modifiers with AFFINITY/ALIGNED/DEVICE (PR #117786)

llvmbot wrote: @llvm/pr-subscribers-flang-semantics Author: Krzysztof Parzyszek (kparzysz) Changes This is a mostly mechanical change from specific modifiers embedded directly in a clause to the Modifier variant. Additional comments and references to the OpenMP specs were added. --- Pa

[llvm-branch-commits] [flang] [flang][OpenMP] Use new modifiers with AFFINITY/ALIGNED/DEVICE (PR #117786)

llvmbot wrote: @llvm/pr-subscribers-flang-parser Author: Krzysztof Parzyszek (kparzysz) Changes This is a mostly mechanical change from specific modifiers embedded directly in a clause to the Modifier variant. Additional comments and references to the OpenMP specs were added. --- Patch

[llvm-branch-commits] [flang] [MLIR][OpenMP] Add Lowering support for OpenMP Declare Mapper directive (PR #117046)

@@ -2701,7 +2701,42 @@ static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, semantics::SemanticsContext &semaCtx, lower::pft::Evaluation &eval, const parser::OpenMPDeclareMapperConstruct &declareMapperConstruct) { - TODO(converter.getC

[llvm-branch-commits] [clang] [flang] [lld] [llvm] [Flang] LLVM_ENABLE_RUNTIMES=flang-rt (PR #110217)

jeanPerier wrote: > Exceptions are unconditionally disabled in `cmake/modules/AddFlangRT.cmake`: > https://github.com/llvm/llvm-project/pull/110217/files#diff-be23c742c88da2fe1ce8d045ad3e39bed2c26ee02ffadcb4c04db40a4857cb55R70 Ah, this only changes for the CUDA build then (using `-DFLANG_RT_E

[llvm-branch-commits] [llvm] AMDGPU: Handle f32 minimum3/maximum3 pattern for gfx950 (PR #117737)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117737 None >From e109d7dbf889634f1af55769aed6e3f9df11f259 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 23 May 2024 21:23:16 +0200 Subject: [PATCH] AMDGPU: Handle f32 minimum3/maximum3 pattern for gfx950 -

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for: v_cvt_scalef32_[f16|f32]_[bf8|fp8] (PR #117739)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117739 OPSEL[1:0] collectively decide which byte to read from src input. Builtin takes additional imm argument which represents index (with valid values:[0:3]) of src byte read. Out of bounds checks will added in next p

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_{fp8|bf8}_f32 for gfx950 (PR #117740)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117740 OPSEL[3] determines low/high 16 bits of word to write. Co-authored-by: Pravin Jagtap >From 60c4d952ee711e23ec80c6d0b64e3c2fd2b58748 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Wed, 17 Apr 2024 09:24:32

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scale_fp4<->f32 for gfx950 (PR #117743)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117743 OPSEL ASM Syntax for v_cvt_scalef32_pk_f32_fp4 : opsel:[x,y,z] where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read. OPSEL ASM Syntax for v_cvt_scalef32_pk_fp4_f32 : opsel:[a,b,c,d] where, c & d i.e. OPS

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{f|bf}16_fp4 for gfx950 (PR #117744)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117744 OPSEL ASM Syntax for v_cvt_scalef32_pk_{f|bf}16_fp4 : opsel:[x,y,z] where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read. Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax. Co-authored-

[llvm-branch-commits] [clang] [llvm] Builtins & Codegen support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 for gfx950 (PR #117742)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117742 OPSEL[3] determines low/high 16 bits of word to write. Co-authored-by: Pravin Jagtap >From a6099c680697a821a486d785ea36fa346d316a33 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 19 Apr 2024 03:09:43

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk32_f32_[fp|bf]6 for gfx950 (PR #117745)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117745 Co-authored-by: Pravin Jagtap >From 57f45c2dd6ac75e67350a46456cb5bed54123d19 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Mon, 22 Apr 2024 04:45:35 -0400 Subject: [PATCH] AMDGPU: Builtin & CodeGen support

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_f32_{fp8|bf8} for gfx950 (PR #117741)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117741 OPSEL[0] determines low/high 16 bits of src0 to read. Co-authored-by: Pravin Jagtap >From 8f2c64c1b0ade2a055ec958f203706f37fc85338 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Thu, 18 Apr 2024 01:18:49 -

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_f32_{fp8|bf8} for gfx950 (PR #117741)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117741?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] Builtins & Codegen support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 for gfx950 (PR #117742)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117742?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scale_fp4<->f32 for gfx950 (PR #117743)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117743?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{f|bf}16_fp4 for gfx950 (PR #117744)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117744?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk32_f32_[fp|bf]6 for gfx950 (PR #117745)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117745?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for: v_cvt_scalef32_[f16|f32]_[bf8|fp8] (PR #117739)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117739 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Make v2f16 minimum/maximum legal for gfx950 (PR #117738)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117738?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Handle f32 minimum3/maximum3 pattern for gfx950 (PR #117737)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117737?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Handle f32 minimum3/maximum3 pattern for gfx950 (PR #117737)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117737 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for: v_cvt_scalef32_[f16|f32]_[bf8|fp8] (PR #117739)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117739?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_{fp8|bf8}_f32 for gfx950 (PR #117740)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117740?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [compiler-rt] [TySan] Fix struct access with different bases (PR #108385)

https://github.com/gbMattN updated https://github.com/llvm/llvm-project/pull/108385 >From 4f5a7f198988a45fe64b9d1ba88e68a6d7f14e32 Mon Sep 17 00:00:00 2001 From: Matthew Nagy Date: Thu, 12 Sep 2024 12:36:57 + Subject: [PATCH 1/3] [TySan] Fix struct access with different bases --- compiler

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & codegen support for v_cvt_scalef32_pk32_{bf|f}16_{bf|fp}6 for gfx950 (PR #117747)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117747 Co-authored-by: Pravin Jagtap >From 0f620e47d5912cde72a2802b34fcba0426eccce0 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Mon, 22 Apr 2024 05:29:12 -0400 Subject: [PATCH] AMDGPU: Builtin & codegen support

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_f32_{fp8|bf8} for gfx950 (PR #117741)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117741 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] Builtins & Codegen support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 for gfx950 (PR #117742)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117742 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Make v2f16 minimum/maximum legal for gfx950 (PR #117738)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117738 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_f32_{fp8|bf8} for gfx950 (PR #117741)

llvmbot wrote: @llvm/pr-subscribers-llvm-ir @llvm/pr-subscribers-clang Author: Matt Arsenault (arsenm) Changes OPSEL[0] determines low/high 16 bits of src0 to read. Co-authored-by: Pravin Jagtap --- Full diff: https://github.com/llvm/llvm-project/pull/117741.diff

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