On 07/30/2018 09:26 AM, Eugeniy Paltsev wrote:
> The ARC HS processor provides an IOC port (I/O coherency bus
> interface) that allows external devices such as DMA devices
> to access memory through the cache hierarchy, providing
> coherency between I/O transactions and the complete memory
> hierar
On 07/30/2018 09:26 AM, Eugeniy Paltsev wrote:
> @@ -1263,11 +1254,7 @@ void __init arc_cache_init_master(void)
> if (is_isa_arcv2() && ioc_enable)
> arc_ioc_setup();
>
> - if (is_isa_arcv2() && ioc_enable) {
> - __dma_cache_wback_inv = __dma_cache_wback_inv_io
On Mon, 2018-08-13 at 16:24 +, Vineet Gupta wrote:
> On 07/30/2018 09:26 AM, Eugeniy Paltsev wrote:
> > @@ -1263,11 +1254,7 @@ void __init arc_cache_init_master(void)
> > if (is_isa_arcv2() && ioc_enable)
> > arc_ioc_setup();
> >
> > - if (is_isa_arcv2() && ioc_enable) {
> >
On Mon, 2018-08-13 at 16:19 +, Vineet Gupta wrote:
> On 07/30/2018 09:26 AM, Eugeniy Paltsev wrote:
> > The ARC HS processor provides an IOC port (I/O coherency bus
> > interface) that allows external devices such as DMA devices
> > to access memory through the cache hierarchy, providing
> > co
On 08/13/2018 10:27 AM, Eugeniy Paltsev wrote:
>> You didn't pay attention to my previous comment on this !
>> IOC port can be considered a micro-architecture optimization (an important
>> one
>> though). The main thing is hardware snooping DMA transactions which enabled
>> IOC in
>> first place.
