On Thu, May 25, 2023 at 8:13 AM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3):
> Retract excessive line folding, and correct the value of
> the "length" insn attribute related to TARGET_DENSITY.
> (*extz
On Thu, May 25, 2023 at 8:13 AM Takayuki 'January June' Suwa
wrote:
>
> This patch makes try to eliminate using temporary pseudo for
> '(minus:SI (const_int) (reg:SI))' if the addition of negative constant
> value can be emitted in a single machine instruction.
>
> /* example */
> int test
On Thu, May 25, 2023 at 8:13 AM Takayuki 'January June' Suwa
wrote:
>
> In order to reject voodoo estimation logic with lots of magic numbers,
> this patch revises the code to measure the costs of the three memset
> methods based on the actual emission size of the insn sequence
> corresponding to
Hi Suwa-san,
On Tue, May 30, 2023 at 2:51 AM Takayuki 'January June' Suwa
wrote:
>
> Resubmitting the correct one due to a mistake in merging order of fixes.
> ---
> This patch introduces more optimized implementations for the 6 cstoresi4
> insn comparison methods (eq/ne/lt/le/gt/ge, however, req
On Tue, May 30, 2023 at 2:50 AM Takayuki 'January June' Suwa
wrote:
>
> Resubmitting the correct one due to a mistake in merging order of fixes.
> ---
> More optimized than the default RTL generation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (adddi3, subdi3):
> New RTL gene
On Tue, May 30, 2023 at 2:27 AM Takayuki 'January June' Suwa
wrote:
>
> The insn "*shlrd_reg" shifts two registers with a funnel shifter by the
> third register to get a single word result:
>
> reg0 = (reg1 SHIFT_OP0 reg3) BIT_JOIN_OP (reg2 SHIFT_OP1 (32 - reg3))
>
> where the funnel left shift
On Wed, May 31, 2023 at 11:01 PM Takayuki 'January June' Suwa
wrote:
> More optimized than the default RTL generation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (adddi3, subdi3):
> New RTL generation patterns implemented according to the instruc-
> tion idioms descri
On Wed, May 31, 2023 at 11:01 PM Takayuki 'January June' Suwa
wrote:
> More optimized than the default RTL generation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (adddi3, subdi3):
> New RTL generation patterns implemented according to the instruc-
> tion idioms descri
Hi Suwa-san,
On Sat, Jun 3, 2023 at 2:55 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation of EQ/NE against zero
> by adding two insn_and_split patterns similar to SImode conditional
> store:
>
> "eq_zero":
> op0 = (op1 == 0) ? 1 : 0;
> op0 = c
On Sat, Jun 3, 2023 at 3:52 PM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes both the boolean evaluation of and the branching of
> EQ/NE against INT_MIN (-2147483648), by taking advantage of the specifi-
> cation the ABS machine instruction on Xtensa returns INT_MIN iff INT_MIN,
> o
Hi Suwa-san,
On Mon, Jun 5, 2023 at 2:37 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation of EQ/NE against zero
> by adding two insn_and_split patterns similar to SImode conditional
> store:
>
> "eq_zero":
> op0 = (op1 == 0) ? 1 : 0;
> op0 = c
On Mon, Jun 5, 2023 at 8:15 AM Max Filippov wrote:
>
> Hi Suwa-san,
>
> On Mon, Jun 5, 2023 at 2:37 AM Takayuki 'January June' Suwa
> wrote:
> >
> > This patch optimizes the boolean evaluation of EQ/NE against zero
> > by adding two insn_and_split patterns similar to SImode conditional
> > store:
On Thu, Jul 20, 2023 at 7:37 AM Alexey Lapshin
wrote:
>
> gcc/
> * config/xtensa/xtensa.h (XCHAL_HAVE_BE, XCHAL_HAVE_DENSITY,
> XCHAL_HAVE_CONST16, XCHAL_HAVE_ABS, XCHAL_HAVE_ADDX,
> XCHAL_HAVE_L32R, XSHAL_USE_ABSOLUTE_LITERALS,
> XSHAL_HAVE_TEXT_SECTION_LITER
On Thu, Jul 20, 2023 at 8:12 AM Alexey Lapshin
wrote:
>
> Oops, missed this loop while implementing...
>
> I had a problem with building esp chips multilib until added my changes.
>
> This loop looks like just defines a macro without value.
But it defines them with their respective values.
Just n
On Thu, Jul 20, 2023 at 9:10 AM Alexey Lapshin
wrote:
> I see now, thanks for the explanation, I will try to rebuild toolchain
> without this particular patch.
> BTW, what do you thing about placing config from newlib overlay to dynconfig?
That's the right thing to do. Bonus points for keeping b
On Thu, Jul 20, 2023 at 10:45 AM Alexey Lapshin
wrote:
>
> On Thu, 2023-07-20 at 08:25 -0700, Max Filippov wrote:
> > But it defines them with their respective values.
> > Just notice that it adds two leading underscores in front of the names.
>
> Why builtin macros were defined with prefix?
> Wit
On Thu, Jul 20, 2023 at 10:54 AM Alexey Lapshin
wrote:
> Please consider to review another two pathes then.
> This would be nice to have it in upstream
Sure, it's going to take some time though as I need to take a good look,
and maybe I'll come back with some change proposals.
--
Thanks.
-- Max
On Wed, Jul 13, 2022 at 4:41 AM Takayuki 'January June' Suwa
wrote:
>
> This patch fixes an non-fatal issue about negative constant values derived
> from FP constant synthesis on hosts whose 'long' is wider than 'int32_t'.
>
> And also replaces the dedicated code in FP constant synthesis split
> p
On Fri, Jul 15, 2022 at 4:17 PM Takayuki 'January June' Suwa
wrote:
>
> This patch allows the constant synthesis to choose shorter instruction
> if possible.
>
> /* example */
> int test(void) {
> return 128 << 8;
> }
>
> ;; before
> test:
> movia2, 0x100
>
On Fri, Jul 15, 2022 at 4:17 PM Takayuki 'January June' Suwa
wrote:
>
> This patch enhances the effectiveness of the previously posted one:
> "xtensa: Optimize bitwise AND operation with some specific forms of
> constants".
>
> /* example */
> extern void foo(int);
> void test(int a)
On Mon, Jul 18, 2022 at 5:47 AM Takayuki 'January June' Suwa
wrote:
>
> This patch corrects the overestimation of the relative cost of
> '(set (reg) (const_int N))' where N fits into the instruction itself.
>
> In fact, such overestimation confuses the RTL loop invariant motion pass.
> As a result
On Fri, Jul 22, 2022 at 4:18 AM Takayuki 'January June' Suwa
wrote:
>
> The RTL combiner will transform "if ((x & C) == C) goto label;"
> into "if ((~x & C) == 0) goto label;" and will try to match it with
> the insn patterns.
...
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*masktrue
On Fri, Jul 29, 2022 at 12:34 PM Takayuki 'January June' Suwa
wrote:
>
> It takes one machine instruction for both condtional branch and move.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_rtx_costs):
> Add new case for IF_THEN_ELSE.
> ---
> gcc/config/xtensa/xtensa.cc
On Fri, Jul 29, 2022 at 12:34 PM Takayuki 'January June' Suwa
wrote:
>
> The hard register A10 was already allocated for EH_RETURN_STACKADJ_RTX.
> (although exception handling and sibling call may not apply at the same time,
> but for safety)
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.
On Sun, Jun 18, 2023 at 12:10 AM Takayuki 'January June' Suwa
wrote:
>
> It used to always return a constant 4, which is same as the default
> behavior, but doesn't take into account the effects of secondary
> reloads.
>
> Therefore, the implementation of this target hook is removed.
>
> gcc/Chang
On Sun, Jun 18, 2023 at 12:10 AM Takayuki 'January June' Suwa
wrote:
>
> This patch adds a new 2-instructions constant synthesis pattern:
>
> - A non-negative square value that root can fit into a signed 12-bit:
> => "MOVI(.N) Ax, simm12" + "MULL Ax, Ax, Ax"
>
> Due to the execution cost of t
On Sat, Jul 1, 2023 at 10:21 AM Takayuki 'January June' Suwa
wrote:
>
> Because both smin and smax requiring TARGET_MINMAX are essential to the
> RTL representation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_match_CLAMPS_imms_p):
> Simplify.
> * config/xtensa
On Sat, Jul 1, 2023 at 10:21 AM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*eqne_INT_MIN):
> Add missing ":SI" to the match_operator.
> ---
> gcc/config/xtensa/xtensa.md | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Regtested f
On Mon, Jul 3, 2023 at 5:57 PM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (machine_function, xtensa_expand_prologue):
> Change to use HARD_REG_BIT and its macros.
> * config/xtensa/xtensa.md
> (peephole2: regmove elimination
Hi Suwa-san,
On Thu, Jan 26, 2023 at 7:17 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
On Fri, Feb 17, 2023 at 8:54 PM Takayuki 'January June' Suwa
wrote:
>
> Leaf function often omits saving its return address to the stack slot,
> and this feature often makes debugging very confusing, especially for
> stack dump analysis.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xt
gcc/
PR target/108876
* config/xtensa/xtensa.cc (xtensa_expand_epilogue): Drop emit_use
for A0_REG.
* config/xtensa/xtensa.md (sibcall, sibcall_internal)
(sibcall_value, sibcall_value_internal): Add 'use' expression
for A0_REG.
---
gcc/config/xtensa/
On Wed, Feb 22, 2023 at 7:42 PM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md
> (zero_cost_loop_start, zero_cost_loop_end, loop_end):
> Add missing "SI:" to PLUS RTXes.
> ---
> gcc/config/xtensa/xtensa.md | 12 ++--
> 1 file c
On Wed, Feb 22, 2023 at 7:42 PM Takayuki 'January June' Suwa
wrote:
>
> In commit b2ef02e8cbbaf95fee98be255f697f47193960ec, the sibling call
> insn included (use (reg:SI A0_REG)) to fix the problem, which added
> a USE chain unconditionally to the data flow of register A0 during
> the sibling call
In commit b2ef02e8cbbaf95fee98be255f697f47193960ec, the sibling call
insn included (use (reg:SI A0_REG)) to fix the problem, which added
a USE chain unconditionally to the data flow of register A0 during
the sibling call.
As a result, df_regs_ever_live_p (A0_REG) returns true, so even if
register
This reverts commit b2ef02e8cbbaf95fee98be255f697f47193960ec.
---
gcc/config/xtensa/xtensa.cc | 2 ++
gcc/config/xtensa/xtensa.md | 20 +++-
2 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index 5c1c713e122d
Hi Jakub,
On Thu, Feb 23, 2023 at 2:34 AM Jakub Jelinek wrote:
> The translation PR complains that these 4 messages from xtensa-dynconfig.c
> are marked in po/gcc.pot as c-format (which doesn't allow %qs) while they
> should be gcc-internal-format.
>
> The problem is in the manual translation of
On Fri, Feb 17, 2023 at 8:43 PM Takayuki 'January June' Suwa
wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __builtin_copysig
On Thu, Feb 16, 2023 at 11:54 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
> the save an
On Thu, Feb 23, 2023 at 1:35 AM Max Filippov wrote:
>
> On Wed, Feb 22, 2023 at 7:42 PM Takayuki 'January June' Suwa
> wrote:
> >
> > In commit b2ef02e8cbbaf95fee98be255f697f47193960ec, the sibling call
> > insn included (use (reg:SI A0_REG)) to fix the problem, which added
> > a USE chain uncond
gcc/
* config/xtensa/xtensa-dynconfig.cc (config.h, system.h)
(coretypes.h, diagnostic.h, intl.h): Use "..." instead of <...>
for the gcc-internal headers.
---
gcc/config/xtensa/xtensa-dynconfig.cc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
gcc/
* config/xtensa/t-xtensa (xtensa-dynconfig.o): Use $(COMPILE)
and $(POSTCOMPILE) instead of manual dependency listing.
* config/xtensa/xtensa-dynconfig.c: Rename to ...
* config/xtensa/xtensa-dynconfig.cc: ... this.
---
gcc/config/xtensa/t-xtensa
gcc/
PR target/108919
* config/xtensa/xtensa-protos.h
(xtensa_prepare_expand_call): Rename to xtensa_expand_call.
* config/xtensa/xtensa.cc (xtensa_prepare_expand_call): Rename
to xtensa_expand_call.
(xtensa_expand_call): Emit the call and add a clob
Hi Suwa-san,
On Sat, Feb 25, 2023 at 3:33 AM Takayuki 'January June' Suwa
wrote:
> On 2023/02/25 19:01, Max Filippov wrote:
> > diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
> > index e52fba082550..babe7f0ebd68 100644
> > --- a/gcc/config/xtensa/xtensa.cc
> > +++ b/gcc/co
gcc/
PR target/108919
* config/xtensa/xtensa-protos.h
(xtensa_prepare_expand_call): Rename to xtensa_expand_call.
* config/xtensa/xtensa.cc (xtensa_prepare_expand_call): Rename
to xtensa_expand_call.
(xtensa_expand_call): Emit the call and add a clob
On Sun, Feb 26, 2023 at 9:27 AM Takayuki 'January June' Suwa
wrote:
> This patch introduces the use of CLAMPS instruction when the instruction
> is configured.
Testing.
> (Totally off-topic, but do you know anything about the SALT/SALTU
> instructions?
> I see them in the "Core Architecture Ins
gcc/
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v2)
(xtensa_get_config_v3): New functions.
include/
* xtensa-dynconfig.h (xtensa_config_v3): New struct.
(xtensa_get_config_v3): New declaration.
(XCHAL_HAVE_CLAMPS, XCHAL_HAVE_DEPBITS, XCHAL_HAVE_E
On Sun, Feb 26, 2023 at 9:27 AM Takayuki 'January June' Suwa
wrote:
>
> This patch introduces the use of CLAMPS instruction when the instruction
> is configured.
>
> /* example */
> int test(int a) {
> if (a < -512)
> return -512;
> if (a > 511)
> return 511;
>
gcc/
* config/xtensa/xtensa.h (STRICT_ALIGNMENT): Make it 0 when the
hardware supports both unaligned loads and stores.
---
gcc/config/xtensa/xtensa.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index
gcc/
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New
function.
include/
* xtensa-dynconfig.h (xtensa_config_v4): New struct.
(XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION)
(XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW)
On Sun, Mar 12, 2023 at 5:37 PM Takayuki 'January June' Suwa
wrote:
>
> Because GO_IF_LEGITIMATE_ADDRESS was deprecated a long time ago
> (see commit c6c3dba931548987c78719180e30ebc863404b89).
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.h (REG_OK_STRICT, REG_OK_FOR_INDEX_P,
> REG
gcc/
* config/xtensa/linux.h (TARGET_ASM_FILE_END): New macro.
libgcc/
* config/xtensa/crti.S: Add .note.GNU-stack section on linux.
* config/xtensa/crtn.S: Likewise.
* config/xtensa/lib1funcs.S: Likewise.
* config/xtensa/lib2funcs.S: Likewise.
---
gcc/conf
Hi Suwa-san,
On Tue, Mar 7, 2023 at 10:04 PM Takayuki 'January June' Suwa
wrote:
>
> This patch makes LRA well with some exceptions
> (e.g. MI thunk generation due to pretending reload_completed).
>
> gcc/ChangeLog:
>
> * config/xtensa/constraints.md (R, T, U):
> Change define_con
Hi Suwa-san,
On Mon, May 8, 2023 at 6:38 AM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/constraints.md (R, T, U):
> Change define_constraint to define_memory_constraint.
> * config/xtensa/xtensa.cc
> (xtensa_lra_p, TARGET_LRA_P): Remo
Hi Suwa-san,
On Mon, May 22, 2023 at 12:06 AM Takayuki 'January June' Suwa
wrote:
>
> This patch decreses one machine instruction from "single bit extraction
> with shifting" operation, and tries to eliminate the conditional
> branch if CST2_POW2 doesn't fit into signed 12 bits with the help
> of
On Mon, May 22, 2023 at 10:48 PM Takayuki 'January June' Suwa
wrote:
>
> On 2023/05/23 11:27, Max Filippov wrote:
> > Hi Suwa-san,
>
> Hi!
>
> > This change introduces a bunch of test failures on big endian configuration.
> > I believe that's because the starting bit position for zero_extract is
On Mon, May 22, 2023 at 12:06 AM Takayuki 'January June' Suwa
wrote:
>
> By making use of the 'addsub_operator' added in the last patch.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*addsubx): Rename from '*addx',
> and change to also accept '*subx' pattern.
> (*subx):
On Mon, Sep 12, 2022 at 8:00 PM Takayuki 'January June' Suwa
wrote:
> On 2022/09/13 4:34, Max Filippov wrote:
> > On Sun, Sep 11, 2022 at 1:50 PM Takayuki 'January June' Suwa
> > wrote:
> >>
> >> This patch implements new target hook TARGET_CONSTANT_OK_FOR_CPROP_P in
> >> order to exclude CONST_I
Suwa-san, could you please take a look?
This change fixes the fowllowing testsuite failures when building for
call0 ABI:
g++.dg/ipa/pr60640-4.C
g++.dg/ipa/pr83549.C
g++.dg/ipa/pr83667.C
g++.dg/torture/pr81812.C
gcc/
* config/xtensa/xtensa.cc (xtensa_can_output_mi_thunk)
(xtensa_o
gcc/
* config/xtensa/xtensa.cc (TARGET_MAX_ANCHOR_OFFSET): New
definition.
---
gcc/config/xtensa/xtensa.cc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index e5abd356a745..828c7642b7cb 100644
--- a/gcc/config/xtens
On Tue, Sep 13, 2022 at 2:58 PM Max Filippov wrote:
>
> Suwa-san, could you please take a look?
>
> This change fixes the fowllowing testsuite failures when building for
> call0 ABI:
>
> g++.dg/ipa/pr60640-4.C
> g++.dg/ipa/pr83549.C
> g++.dg/ipa/pr83667.C
> g++.dg/torture/pr81812.C
>
> gcc/
>
Hi Suwa-san,
On Fri, Oct 14, 2022 at 4:19 AM Takayuki 'January June' Suwa
wrote:
> This patch provides the first step in the transition from Reload to LRA
> in Xtensa.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa-proto.h (xtensa_split1_is_finished_p):
> New prototype.
> *
On Mon, Oct 17, 2022 at 7:57 PM Takayuki 'January June' Suwa
wrote:
> On 2022/10/16 14:03, Max Filippov wrote:
> > There's also the following runtime failures, but only on call0
> > configuration:
> >
> > +FAIL: gcc.c-torture/execute/20010122-1.c -O1 execution test
> > +FAIL: gcc.c-torture/exe
Hi Suwa-san,
v2 fixes the regressions caused by ICEs, but not the runtime failures.
On Mon, Oct 17, 2022 at 8:14 PM Max Filippov wrote:
> On Mon, Oct 17, 2022 at 7:57 PM Takayuki 'January June' Suwa
> wrote:
> > On 2022/10/16 14:03, Max Filippov wrote:
> > > There's also the following runtime f
On Wed, Oct 19, 2022 at 1:16 AM Takayuki 'January June' Suwa
wrote:
> This patch provides the first step in the transition from Reload to LRA
> in Xtensa.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa-proto.h
> (xtensa_split1_finished_p, xtensa_split_DI_reg_imm): New prototypes.
>
Hi Suwa-san,
On Thu, Oct 20, 2022 at 7:58 PM Takayuki 'January June' Suwa
wrote:
>
> This patch offers an additional allocable register by RA for the CALL0
> ABI.
>
> > Register a0 holds the return address upon entry to a function, but
> > unlike the windowed register ABI, it is not reserved for
On Fri, Oct 21, 2022 at 3:46 PM Takayuki 'January June' Suwa
wrote:
>
> This patch offers an additional allocable register by RA for the CALL0
> ABI.
>
> > Register a0 holds the return address upon entry to a function, but
> > unlike the windowed register ABI, it is not reserved for this purpose
>
On Tue, Oct 25, 2022 at 11:27 PM Takayuki 'January June' Suwa
wrote:
>
> On 2022/10/26 5:09, Jan-Benedict Glaw wrote:
> > I didn't yet actually check the warning, it may be bogus.
>
> This "problem" can occur in the following two places calling
> xtensa_split_DI_reg_imm():
>
> - (define_expand "m
On Sun, Aug 14, 2022 at 2:31 AM Takayuki 'January June' Suwa
wrote:
>
> Since GCC10, the "subreg2" optimization pass was no longer tied to enabling
> "subreg1" unless -fsplit-wide-types-early was turned on (PR88233). However
> on the Xtensa port, the lack of "subreg2" can degrade the quality of t
Hi Suwa-san,
On Tue, Aug 16, 2022 at 5:42 AM Takayuki 'January June' Suwa
wrote:
>
> In a few cases, obviously omitable add instructions can be emitted via
> invoking gen_addsi3.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (addsi3_internal): Rename from "addsi3".
> (addsi3):
On Wed, Aug 17, 2022 at 2:52 AM Takayuki 'January June' Suwa
wrote:
> As a matter of fact, "in a few cases" is just only one:
>
> [xtensa_expand_epilogue() in /gcc/config/xtensa/xtensa.cc]
> > if (cfun->machine->current_frame_size > 0)
> > {
> > if (frame_pointer_needed || /* al
On Wed, Aug 17, 2022 at 12:32 PM Takayuki 'January June' Suwa
wrote:
>
> This patch enforces the use of "addmi" machine instruction instead of
> addition/subtraction with two source registers for adjusting the stack
> pointer, if the adjustment fits into a signed 16-bit and is also a multiple
> of
On Thu, Aug 18, 2022 at 3:06 AM Takayuki 'January June' Suwa
wrote:
>
> No longer needs the dedicated hard register (A11) for the address of the
> call and the split patterns for fixups, due to the introduction of appropriate
> register class and constraint.
>
> (Note: "ISC_REGS" contains a hard r
Hi Suwa-san,
On Fri, Sep 2, 2022 at 3:57 AM Takayuki 'January June' Suwa
wrote:
>
> Changes from v1:
> (xtensa_expand_epilogue): Fixed forgetting to consider
> hard_frame_pointer_rtx when sharing codes.
>
> ---
> In the example below, 'x' is once placed on the stack frame and then read
> into
gcc/
* config/xtensa/linux.h (LINK_SPEC): Add static-pie.
---
gcc/config/xtensa/linux.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gcc/config/xtensa/linux.h b/gcc/config/xtensa/linux.h
index 540e4bf538f8..bc7bee71517d 100644
--- a/gcc/config/xtensa/linux.h
+++
Hi Suwa-san,
On Wed, Sep 7, 2022 at 2:08 AM Takayuki 'January June' Suwa
wrote:
>
> Changes from v2:
> (xtensa_expand_prologue): Changed to check conditions for suppressing emit
> insns in advance, instead of tracking emitted and later replacing them with
> NOPs if they are found to be unnece
On Thu, Sep 8, 2022 at 2:38 PM Takayuki 'January June' Suwa
wrote:
>
> Changes from v3:
> (xtensa_expand_prologue): Changed to exclude debug insns from DF use chain
> analysis.
>
> ---
>
> In the example below, 'x' is once placed on the stack frame and then read
> into registers as the argument
On Wed, Aug 31, 2022 at 10:50 PM Takayuki 'January June' Suwa
wrote:
>
> This patch eliminates all clobbers for complex hard registers that will
> be overwritten entirely afterwards (supersedence of
> 3867d414bd7d9e5b6fb2a51b1fb3d9e9e1eae9).
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md
On Sat, Sep 10, 2022 at 2:44 AM Takayuki 'January June' Suwa
wrote:
>
> This patch adds a new 3-instructions constant synthesis pattern:
>
> - A value that can fit into a signed 12-bit after a number of either bitwise
> left or right rotations:
> => "MOVI(.N) Ax, simm12" + "SSAI (1 ... 11) o
xtensa may use up to 4 registers to return a value from a function, but
recognition of only one register in the xtensa_function_value_regno_p
and missing untyped_call pattern result in that only one register is
saved by the __builtin_apply and returned by the __builtin_apply_return.
gcc/
*
On Sun, Sep 11, 2022 at 1:50 PM Takayuki 'January June' Suwa
wrote:
>
> This patch implements new target hook TARGET_CONSTANT_OK_FOR_CPROP_P in
> order to exclude CONST_INTs that cannot fit into a MOVI machine instruction
> from cprop.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.c (TARGE
On Fri, May 6, 2022 at 3:37 AM Takayuki 'January June' Suwa via
Gcc-patches wrote:
>
> These patterns were deprecated since GCC 4.8.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (extvsi, extvsi_internal, extzvsi,
> extzvsi_internal): Rename from extv, extv_internal, extzv and
>
On Fri, May 6, 2022 at 3:36 AM Takayuki 'January June' Suwa via
Gcc-patches wrote:
>
> On Espressif's ESP8266 (based on Tensilica LX106, no hardware divider),
> this patch reduces the size of each:
>
>__moddi3() @ libgcc.a : 969 -> 301 (saves 668)
>__divmoddi4() : -> 426 (sav
2021-09-07 Takayuki 'January June' Suwa
gcc/
PR target/102115
* config/xtensa/xtensa.c (xtensa_emit_move_sequence): Add
'CONST_INT_P (src)' to the condition of the block that tries to
eliminate literal when loading integer contant.
---
gcc/config/xtensa/xtensa.c
2021-09-14 Max Filippov
gcc/
PR target/102336
* config/xtensa/t-xtensa (TM_H): Add include/xtensa-config.h.
---
gcc/config/xtensa/t-xtensa | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config/xtensa/t-xtensa b/gcc/config/xtensa/t-xtensa
index 973815c8c2d6..d06e49280545
On Wed, Jun 2, 2021 at 11:27 AM Jeff Law wrote:
> On 6/2/2021 11:09 AM, Jakub Jelinek wrote:
> > When building gcc targetting xtensa-linux, there are 2 warnings the PR
> > complains about:
> > ../../gcc/dwarf2cfi.c: In function ‘void init_one_dwarf_reg_size(int,
> > machine_mode, rtx, machine_mod
On Mon, Dec 26, 2022 at 10:30 PM Takayuki 'January June' Suwa
wrote:
>
> Almost cosmetic and no functional changes.
>
> gcc/ChangeLog:
>
> * config/xtensa/*: Tabify, and trim trailing spaces.
> * config/xtensa/xtensa.h (GP_RETURN, GP_RETURN_REG_COUNT):
> Change to GP_RETURN
From: Takayuki 'January June' Suwa
gcc/ChangeLog:
* config/xtensa/xtensa.md (set_frame_ptr): Fix to reflect
TARGET_DENSITY.
---
gcc/config/xtensa/xtensa.md | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/
From: Takayuki 'January June' Suwa
gcc/ChangeLog:
* config/xtensa/xtensa.h (GP_RETURN, GP_RETURN_REG_COUNT):
Change to GP_RETURN_FIRST and GP_RETURN_LAST, respectively.
* config/xtensa/xtensa.cc (xtensa_function_value,
xtensa_libcall_value, xtensa_function_value_r
From: Takayuki 'January June' Suwa
gcc/ChangeLog:
* config/xtensa/xtensa.cc (xtensa_expand_prologue): Modify to
exit the inspection loops as soon as the necessity of stack
pointer is found.
---
gcc/config/xtensa/xtensa.cc | 10 --
1 file changed, 8 insertions(+),
This improves RTL dumps readability. No functional changes.
gcc/
* config/xtensa/xtensa.md (unspec): Extract UNSPEC_* constants
into this enum.
(unspecv): Extract UNSPECV_* constants into this enum.
---
gcc/config/xtensa/xtensa.md | 46 -
From: Takayuki 'January June' Suwa
Cosmetic and no functional changes.
gcc/ChangeLog:
* config/xtensa/elf.h: Tabify, and trim trailing spaces.
* config/xtensa/linux.h: Likewise.
* config/xtensa/uclinux.h: Likewise.
* config/xtensa/xtensa-dynconfig.c: Likewise.
On Thu, Dec 29, 2022 at 4:33 AM Takayuki 'January June' Suwa
wrote:
>
> Parhaps no problem, but for safety.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_expand_prologue): Fix to check
> DF availability before use of DF_* macros.
> ---
> gcc/config/xtensa/xtensa.cc | 2
gcc/
* config/xtensa/xtensa.cc (xtensa_return_in_memory): Use
GP_RETURN_* instead of magic constant.
---
gcc/config/xtensa/xtensa.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index e726a115029f..ae4
Hi Suwa-san,
On Thu, Jan 5, 2023 at 3:57 AM Takayuki 'January June' Suwa
wrote:
>
> This patch introduces a convenient helper function for integer immediate
> addition with scratch register as needed, that splits and emits either
> up to two ADDI/ADDMI machine instructions or an addition by regis
On Thu, Jan 5, 2023 at 7:35 PM Takayuki 'January June' Suwa
wrote:
> On second thought, it cannot be a good idea to split addition/subtraction to
> the stack pointer.
>
> > -4aaf: b0a192 movia9, 0x1b0
> > -4ab2: 1f9aadd.n a1, a15, a9
>
> > +4aaf:
On Thu, Jan 5, 2023 at 10:57 PM Takayuki 'January June' Suwa
wrote:
> By using the helper function, it makes stack frame adjustment logic
> simplified and instruction count less in some cases.
I've built a couple linux configurations with and without this change and
I observe consistent code size
On Fri, Jan 6, 2023 at 6:55 PM Takayuki 'January June' Suwa
wrote:
>
> This patch introduces a convenient helper function for integer immediate
> addition with scratch register as needed, that splits and emits either
> up to two ADDI/ADDMI machine instructions or an addition by register
> followin
On Fri, Jan 6, 2023 at 6:55 PM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the operation of cutting and splicing two register
> values at a specified bit position, in other words, combining (bitwise
> ORing) bits 0 through (C-1) of the register with bits C through 31
> of the othe
On Sat, Jan 7, 2023 at 9:04 PM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the operation of cutting and splicing two register
> values at a specified bit position, in other words, combining (bitwise
> ORing) bits 0 through (C-1) of the register with bits C through 31
> of the othe
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