[PATCH] match.pd: Only merge truncation with conversion for -fno-signed-zeros

This optimisation does not honour signed zeros, so should not be enabled except with -fno-signed-zeros. OK for master? I do not have commit rights for GCC, so if the patch is fine would someone be able to commit for me? The bug is present in all GCC versions from 12.1.0 onwards - is it possible to

[PATCH v2] match.pd: Only merge truncation with conversion for -fno-signed-zeros

This optimisation does not honour signed zeros, so should not be enabled except with -fno-signed-zeros. OK for master? I do not have commit rights for GCC, so if the patch is fine would someone be able to commit for me? The bug is present in all GCC versions from 12.1.0 onwards - is it possible to

[PATCH][Backport][GCC12] match.pd: Only merge truncation with conversion for -fno-signed-zeros

This optimisation does not honour signed zeros, so should not be enabled except with -fno-signed-zeros. Cherry-pick of 7dd3b2b09cbeb6712ec680a0445cb0ad41070423. Applies cleanly on releases/gcc-12. Regression-tested, only new failure is in gcc/testsuite/c-c++-common/hwasan/large-aligned-1.c which

[PATCH][Backport][GCC13] match.pd: Only merge truncation with conversion for -fno-signed-zeros

This optimisation does not honour signed zeros, so should not be enabled except with -fno-signed-zeros. Cherry-pick of 7dd3b2b09cbeb6712ec680a0445cb0ad41070423. Applies cleanly on releases/gcc-13, regression-tested with no new failures. OK for backport to GCC 13? If so, please commit for me as I

[PATCH] arm: Add +nomve and +nomve.fp options to -mcpu=cortex-m55

From: Joe Ramsay Hi, This patch rearranges feature bits for MVE and FP to implement the following flags for -mcpu=cortex-m55. - +nomve:equivalent to armv8.1-m.main+fp.dp+dsp. - +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp (+dsp is implied by +mve). - +nofp: equivalent to

[PATCH] arm: Remove coercion from scalar argument to vmin & vmax intrinsics

From: Joe Ramsay Hi, This patch fixes an issue with vmin* and vmax* intrinsics which accept a scalar argument. Previously when the scalar was of different width to the vector elements this would generate __ARM_undef. This change allows the scalar argument to be implicitly converted to the

[PATCH] arm: Require MVE memory operand for destination of vst1q intrinsic

From: Joe Ramsay Hi, Previously, the machine description patterns for vst1q accepted a generic memory operand for the destination, which could lead to an unrecognised builtin when expanding vst1q* intrinsics. This change fixes the patterns to only accept MVE memory operands. Tested on arm-none

[PATCH v2][GCC] arm: Add +nomve and +nomve.fp options to -mcpu=cortex-m55

From: Joe Ramsay Hi all, This patch rearranges feature bits for MVE and FP to implement the following flags for -mcpu=cortex-m55. - +nomve:equivalent to armv8.1-m.main+fp.dp+dsp. - +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp (+dsp is implied by +mve). - +nofp: equivalent to

Re: [PATCH] arm: Require MVE memory operand for destination of vst1q intrinsic

Hi Ramana, Thanks for the review. On 18/08/2020, 18:37, "Ramana Radhakrishnan" wrote: On Thu, Aug 13, 2020 at 2:18 PM Joe Ramsay wrote: > > From: Joe Ramsay > > Hi, > > Previously, the machine description patterns for vst1

[PATCH][GCC][GCC-10 backport] arm: Require MVE memory operand for destination of vst1q intrinsic

From: Joe Ramsay Hi, Previously, the machine description patterns for vst1q accepted a generic memory operand for the destination, which could lead to an unrecognised builtin when expanding vst1q* intrinsics. This change fixes the pattern to only accept MVE memory operands. Tested on arm-none

[PATCH]: Optimize a >= 0 && b >= 0 to (a | b) >= 0 [PR95731]

Hi! This is a fix for PR95731, which adds a new pattern to simplify a >= 0 && b >= 0 to (a | b) >= 0. Bootstrapped and tested on x86_linux and aarch64_linux. Any comments are appreciated. Thanks, Joe gcc/ChangeLog: 2020-05-20 Joe Ramsay * match.pd: New pattern t

[PATCH v2]: Optimize a >= 0 && b >= 0 to (a | b) >= 0 [PR95731]

angeLog: 2020-05-20 Joe Ramsay mailto:joe.ram...@arm.com>> * match.pd: New simplication. gcc/testsuite/ChangeLog: 2020-05-20 Joe Ramsay mailto:joe.ram...@arm.com>> * gcc.dg/tree-ssa/pr95731-1.c: New test. * gcc.dg/tree-ssa/pr95731-2.c: New test. pr95

[PATCH] [PATCH][GCC] arm: Enable no-writeback vldr.16/vstr.16.

relevant case for vldr.16 and vstr.16 Bootstrapped on arm-linux, gcc and CMSIS-DSP testsuites are clean. Is this patch OK for trunk? If yes, please commit on my behalf as I don't have commit rights. Thanks, Joe gcc/ChangeLog: 2020-05-20 Joe Ramsay * config/arm/arm-pro

Re: [PATCH] [PATCH][GCC] arm: Enable no-writeback vldr.16/vstr.16.

Thanks for the feedback Kyrill. On 28/07/2020, 10:16, "Kyrylo Tkachov" wrote: Hi Joe, > -Original Message- > From: Gcc-patches On Behalf Of Joe > Ramsay > Sent: 27 July 2020 15:08 > To: Jakub Jelinek via Gcc-patches > Subje

[PATCH v2][GCC] arm: Enable no-writeback vldr.16/vstr.16.

case for vldr.16 and vstr.16 Bootstrapped on arm-linux, gcc and CMSIS-DSP testsuites are clean. Is this patch OK for trunk? If yes, please commit on my behalf as I don't have commit rights. Thanks, Joe gcc/ChangeLog: 2020-05-20 Joe Ramsay * config/arm/arm-pro

[committed] MAINTAINERS: Add myself for write after approval

2020-07-30 Joe Ramsay * MAINTAINERS (Write After Approval): Add myself. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 300c10e..0b825c7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -563,6 +563,7 @@ Vladimir Prus

[PATCH][GCC-10 Backport] arm: Enable no-writeback vldr.16/vstr.16.

From: Joe Ramsay Hi, There was previously no way to specify that a register operand cannot have any writeback modifiers, and as a result the argument to vldr.16 and vstr.16 could be erroneously output with post-increment. This change adds a constraint which forbids all writeback, and selects it

[PATCH] aarch64: add support for unpacked EOR, ORR and AND

h, z1.h uxthz0.s, p1/m, z0.s st1wz0.s, p0, [x0] ret Tested on aarch64-linux-gnu and x86_64-linux-gnu hosts. Thanks, Joe 2020-05-20 Joe Ramsay * config/aarch64/aarch64-sve.md (3): Add support for unpacked EOR, ORR, AND. gcc/testsuite/ChangeLog 2020-05-

[PATCH]: aarch64: add support for unpacked EOR, ORR and AND

From: Joe Ramsay Date: Thursday, 28 May 2020 at 16:19 To: Gcc-patches Subject: [PATCH]: aarch64: add support for unpacked EOR, ORR and AND Hi! This patch improves code generation for EOR, ORR and AND on unpacked vectors with SVE. The following function: void f (unsigned int *x, unsigned

[PATCH] AArch64+SVE: Add support for unpacked unary ops and BIC

/aarch64-sve.md (@aarch64_bic): Enable unpacked BIC. * config/aarch64/aarch64-sve-md (*bic3): Enable unpacked BIC. gcc/testsuite/ChangeLog: 2020-05-27 Joe Ramsay * gcc.target/aarch64/sve/logical_unpacked_abs.c: New test. * gcc.target/aarch64/sve/logical_unpacked_bic_1.c: New