On 2024-02-29 09:42, mengqinggang wrote:
Generate la.tls.desc macro instruction for TLS descriptors model.
la.tls.desc expand to
pcalau12i $a0, %desc_pc_hi20(a)
ld.d $a1, $a0, %desc_ld_pc_lo12(a)
addi.d$a0, $a0, %desc_add_pc_lo12(a)
jirl $ra, $a1, %desc_call(a)
Sorry
On 2023-12-08 10:04, chenglulu wrote:
在 2023/12/7 下午8:20, Xi Ruoyao 写道:
There seems no real reason to require -mexplicit-relocs=always for
-mcmodel=extreme or model attribute. As the linker does not know how to
relax a 3-operand la.local or la.global pseudo instruction, just emit
explicit rel
gcc/ChangeLog:
* config/loongarch/sync.md:
Add atomic_cas_value_exchange_and_7 and fix atomic_exchange.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/sync-1.c: New test.
---
gcc/config/loongarch/sync.md| 27 -
gcc/testsuite/gcc.target/loongarch/sync-1.c | 104
On 2022/11/15 下午10:21, Xi Ruoyao wrote:
On Tue, 2022-11-15 at 21:03 +0800, Jinyang He wrote:
gcc/ChangeLog:
* config/loongarch/sync.md:
Add atomic_cas_value_exchange_and_7 and fix atomic_exchange.
nit:
* config/loongarch/sync.md (atomic_cas_value_exchange_and_7):
New
On 2022/11/16 下午7:46, Xi Ruoyao wrote:
On Wed, 2022-11-16 at 10:11 +0800, Jinyang He wrote:
+ return "%G6\\n\\t"
+ "1:\\n\\t"
+ "ll.\\t%0,%1\\n\\t"
+ "and\\t%7,%0,%z3\\n\\t"
+ "or%i5\\t%7,%7,%5\\n\\t"
+ &quo
On 2022/11/17 上午9:39, Jinyang He wrote:
On 2022/11/16 下午7:46, Xi Ruoyao wrote:
On Wed, 2022-11-16 at 10:11 +0800, Jinyang He wrote:
+ return "%G6\\n\\t"
+ "1:\\n\\t"
+ "ll.\\t%0,%1\\n\\t"
+ "and\\t%7,%0,%z3\\n\\t"
+ "
On 2022/11/17 上午11:38, Xi Ruoyao wrote:
On Thu, 2022-11-17 at 10:55 +0800, Jinyang He wrote:
On 2022/11/17 上午9:39, Jinyang He wrote:
On 2022/11/16 下午7:46, Xi Ruoyao wrote:
On Wed, 2022-11-16 at 10:11 +0800, Jinyang He wrote:
+ return "%G6\\n\\t"
+ "1:\\n\\t"
+
We used to expand atomic_exchange_n(ptr, new, mem_order) for subword types
into something like:
{
__typeof__(*ptr) t = atomic_load_n(ptr, mem_order);
atomic_compare_exchange_n(ptr, &t, new, true, mem_order, mem_order);
return t;
}
It's incorrect because another thread ma
For {xv,v}{srl,sll,sra}, the constraint `vector_same_uimm6` cause overflow
in when emit {w,h,b}. Since the number of bits shifted is the remainder of
the register value, it is actually unnecessary to constrain the range.
Simply mask the shift number with the unit-bit-width, without any
constraint o
在 2024/11/27 上午10:14, Xi Ruoyao 写道:
On Tue, 2024-11-26 at 18:37 +0800, Jinyang He wrote:
For {xv,v}{srl,sll,sra}, the constraint `vector_same_uimm6` cause overflow
in when emit {w,h,b}. Since the number of bits shifted is the remainder of
the register value, it is actually unnecessary to
For {xv,v}{srl,sll,sra}, the constraint `vector_same_uimm6` cause overflow
in when emit {w,h,b}. Since the number of bits shifted is the remainder of
the register value, it is actually unnecessary to constrain the range.
Simply mask the shift number with the unit-bit-width, without any
constraint o
For {xv,v}{srl,sll,sra}, the constraint `vector_same_uimm6` cause overflow
in when emit {w,h,b}. Since the number of bits shifted is the remainder of
the register value, it is actually unnecessary to constrain the range.
Simply mask the shift number with the unit-bit-width, without any
constraint o
On 2025-04-03 11:37, Lulu Cheng wrote:
在 2025/4/3 上午11:12, Xi Ruoyao 写道:
On Thu, 2025-04-03 at 10:13 +0800, Lulu Cheng wrote:
在 2025/4/2 上午11:19, Xi Ruoyao 写道:
Avoid using gensub that FreeBSD awk lacks, use gsub and split those
each
of gawk, mawk, and FreeBSD awk provides.
Reported-by: mp..
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