Thanks for the feedback.
Nathan Sidwell writes:
> On 7/14/23 11:56, Richard Sandiford wrote:
>> Summary: We'd like to be able to specify some attributes using
>> keywords, rather than the traditional __attribute__ or [[...]]
>> syntax. Would that be OK?
>>
>> In more detail:
>>
>> We'd like to
Hi,
This is a reworked version (following review) of the patch by Maxim Blinov and
Iain Sandoe enabling heap-based trampolines. What has changed since the last
version:
- wording changes, preferring to use “heap-based trampolines” rather than
“off-stack trampolines”
- the option triggering gen
Jakub Jelinek writes:
> On Fri, Jul 14, 2023 at 04:56:18PM +0100, Richard Sandiford via Gcc-patches
> wrote:
>> Summary: We'd like to be able to specify some attributes using
>> keywords, rather than the traditional __attribute__ or [[...]]
>> syntax. Would that be OK?
>
> Will defer to C/C++ ma
On 15/07/2023 06:55, Ken Matsui via Libstdc++ wrote:
This patch implements built-in trait for std::is_arithmetic.
gcc/cp/ChangeLog:
* cp-trait.def: Define __is_arithmetic.
* constraint.cc (diagnose_trait_expr): Handle CPTK_IS_ARITHMETIC.
* semantics.cc (trait_expr_valu
On 15/07/2023 06:55, Ken Matsui via Libstdc++ wrote:
This patch optimizes the performance of the is_arithmetic trait by
dispatching to the new __is_arithmetic built-in trait.
libstdc++-v3/ChangeLog:
* include/std/type_traits (is_arithmetic): Use __is_arithmetic
built-in trait.
On 15/07/2023 06:55, Ken Matsui via Libstdc++ wrote:
This patch optimizes the performance of the is_fundamental trait by
dispatching to the new __is_arithmetic built-in trait.
libstdc++-v3/ChangeLog:
* include/std/type_traits (is_fundamental_v): Use __is_arithmetic
built-in tr
On Fri, Jul 14, 2023 at 11:16:58AM -0400, Jason Merrill wrote:
> On 6/30/23 23:28, Nathaniel Shead via Gcc-patches wrote:
> > This adds rudimentary lifetime tracking in C++ constexpr contexts,
>
> Thanks!
>
> I'm not seeing either a copyright assignment or DCO certification for you;
> please see
Dear all,
some intrinsics may return character results with the same
characteristics as their first argument (e.g. PACK, MINVAL, ...).
If the first argument is of deferred-length, we need to derive
the character length of the result from the first argument, like
in the assumed-length case, but we
On Sun, Jul 16, 2023 at 10:30:59PM +0200, Harald Anlauf via Fortran wrote:
> Dear all,
>
> some intrinsics may return character results with the same
> characteristics as their first argument (e.g. PACK, MINVAL, ...).
> If the first argument is of deferred-length, we need to derive
> the character
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-14 10:50
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support basic floating-point dynamic rounding mode
From: Pan Li
This patch would like to support the basic floating-point dynamic
ro
On Thu, Jul 13, 2023 at 2:06 PM Haochen Jiang via Gcc-patches
wrote:
>
> From: Kong Lingling
>
> gcc/ChangeLog
>
> * common/config/i386/cpuinfo.h (get_available_features): Detect
> avxvnniint16.
> * common/config/i386/i386-common.cc
> (OPTION_MASK_ISA2_AVXVNNIINT16
On Thu, Jul 13, 2023 at 2:06 PM Haochen Jiang via Gcc-patches
wrote:
>
> gcc/ChangeLog:
>
> * common/config/i386/cpuinfo.h (get_available_features):
> Detect SHA512.
> * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SHA512_SET,
> OPTION_MASK_ISA2_SHA512_UNSET)
On Thu, Jul 13, 2023 at 2:04 PM Haochen Jiang via Gcc-patches
wrote:
>
> gcc/ChangeLog:
>
> * common/config/i386/cpuinfo.h (get_available_features):
> Detect SM3.
> * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM3_SET,
> OPTION_MASK_ISA2_SM3_UNSET): New.
>
On Thu, Jul 13, 2023 at 2:04 PM Haochen Jiang via Gcc-patches
wrote:
>
> gcc/ChangeLog:
>
> * common/config/i386/cpuinfo.h (get_available_features):
> Detech SM4.
> * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM4_SET,
> OPTION_MASK_ISA2_SM4_UNSET): New.
>
On Fri, Jul 14, 2023 at 10:55 AM Mo, Zewei via Gcc-patches
wrote:
>
> Hi all,
>
> This patch is to add initial support for Lunar Lake, Arrow Lake and Arrow Lake
> S for GCC.
>
> This link of related information is listed below:
> https://www.intel.com/content/www/us/en/develop/download/intel-archi
> -Original Message-
> From: Jiang, Haochen
> Sent: Friday, July 14, 2023 10:50 AM
> To: Roger Sayle ; gcc-patches@gcc.gnu.org
> Cc: 'Uros Bizjak'
> Subject: RE: [x86 PATCH] Fix FAIL of gcc.target/i386/pr91681-1.c
>
> > The recent change in TImode parameter passing on x86_64 results in th
Hi,
As PR110652 and its duplicate PRs show, there could be one
build error
error: 'new_temp' may be used uninitialized
for some build configurations. It's a false positive warning
(or error at -Werror), but in order to make the build succeed,
this patch is to initialize the reported variable
This adds the boolean version of some of the simplifications
that were added with r8-4395-ge268a77b59cb78.
That are the following:
(a | b) & (a == b) --> a & b
a | (a == b) --> a | (b ^ 1)
(a & b) | (a == b) --> a == b
OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
gc
Hi all,
This patch adds documentation to wwwdocs to mention the recent introduction
of Intel new ISA and march.
Ok for trunk?
BRs,
Haochen
---
htdocs/gcc-13/changes.html | 4
htdocs/gcc-14/changes.html | 34 +-
2 files changed, 37 insertions(+), 1 deletion
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
Normally, GPR2 is the TOC pointer and is defined as a fixed and non-volatile
register. However, it can be used as volatile for PCREL addressing. Therefore,
modified r2 to be non-fixed in FIXED_REGISTERS and se
On Sun, Jul 16, 2023 at 5:28 AM François Dumont wrote:
>
>
> On 15/07/2023 06:55, Ken Matsui via Libstdc++ wrote:
> > This patch implements built-in trait for std::is_arithmetic.
> >
> > gcc/cp/ChangeLog:
> >
> > * cp-trait.def: Define __is_arithmetic.
> > * constraint.cc (diagnose_tra
On Sun, Jul 16, 2023 at 5:32 AM François Dumont wrote:
>
>
> On 15/07/2023 06:55, Ken Matsui via Libstdc++ wrote:
> > This patch optimizes the performance of the is_arithmetic trait by
> > dispatching to the new __is_arithmetic built-in trait.
> >
> > libstdc++-v3/ChangeLog:
> >
> > * includ
On Sun, Jul 16, 2023 at 5:41 AM François Dumont wrote:
>
>
> On 15/07/2023 06:55, Ken Matsui via Libstdc++ wrote:
> > This patch optimizes the performance of the is_fundamental trait by
> > dispatching to the new __is_arithmetic built-in trait.
> >
> > libstdc++-v3/ChangeLog:
> >
> > * inclu
On Fri, Jul 14, 2023 at 5:40 PM Jan Beulich via Gcc-patches
wrote:
>
> Introduce a new alternative permitting all 32 registers to be used as
> source without AVX512VL, by broadcasting to the full 512 bits in that
> case. (The insn would also permit all registers to be used as
> destination, but V2
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): Report ERROR for
TARGET_MIN_VLEN > 4096
---
gcc/config/riscv/riscv.cc | 8
1 file changed, 8 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6ed735d6983..ce523eea9ba 100644
-
On Fri, Jul 14, 2023 at 5:42 PM Jan Beulich via Gcc-patches
wrote:
>
> In the (however unlikely) event that no insn can be found for the
> requested mode, using maybe_gen_...() without (really) checking its
> result for being a null rtx would lead to silent bad code generation.
Ok.
>
> gcc/
>
>
On Mon, Jul 17, 2023 at 2:05 PM Juzhe-Zhong wrote:
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_option_override): Report ERROR for
> TARGET_MIN_VLEN > 4096
>
> ---
> gcc/config/riscv/riscv.cc | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv
On Fri, Jul 14, 2023 at 8:56 PM Roger Sayle wrote:
>
>
>
> This patch fixes the bootstrap failure I'm seeing using gcc 4.8.5 as
>
> the host compiler. Ok for mainline? [I might be missing something]
OK. Btw, while I didn't spot this during review I would appreciate
if the code could use vec.[
On 17.07.2023 08:09, Hongtao Liu wrote:
> On Fri, Jul 14, 2023 at 5:40 PM Jan Beulich via Gcc-patches
> wrote:
>>
>> Introduce a new alternative permitting all 32 registers to be used as
>> source without AVX512VL, by broadcasting to the full 512 bits in that
>> case. (The insn would also permit a
On Fri, Jul 14, 2023 at 10:56 PM Andrew Pinski via Gcc-patches
wrote:
>
> I had messed up the case where the outer operator is `==`.
> The check for the resulting should have been `==` and not `!=`.
> This patch fixes that and adds a full runtime testcase now for
> all cases to make sure it works.
Hi Andrew, Aldy and Richard,
Thanks a lot for all your very helpful comments!
Andrew MacLeod writes:
> On 7/14/23 09:37, Richard Biener wrote:
>> On Fri, 14 Jul 2023, Aldy Hernandez wrote:
>>
>>> I don't know what you're trying to accomplish here, as I haven't been
>>> following the PR, but a
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): Add TARGET_MIN_VLEN <
4096 check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvl-unimplemented.c: New test.
---
gcc/config/riscv/riscv.cc | 8
.../gcc.target/risc
On Sun, Jul 16, 2023 at 12:39 PM FX Coudert via Gcc-patches
wrote:
>
> Hi,
>
> This is a reworked version (following review) of the patch by Maxim Blinov
> and Iain Sandoe enabling heap-based trampolines. What has changed since the
> last version:
>
> - wording changes, preferring to use “heap-b
On Fri, Jul 14, 2023 at 5:58 PM Richard Sandiford via Gcc-patches
wrote:
>
> Summary: We'd like to be able to specify some attributes using
> keywords, rather than the traditional __attribute__ or [[...]]
> syntax. Would that be OK?
>
> In more detail:
>
> We'd like to add some new target-specifi
On Mon, Jul 17, 2023 at 4:22 AM Kewen.Lin wrote:
>
> Hi,
>
> As PR110652 and its duplicate PRs show, there could be one
> build error
>
> error: 'new_temp' may be used uninitialized
>
> for some build configurations. It's a false positive warning
> (or error at -Werror), but in order to make th
On Mon, Jul 17, 2023 at 4:43 AM Andrew Pinski via Gcc-patches
wrote:
>
> This adds the boolean version of some of the simplifications
> that were added with r8-4395-ge268a77b59cb78.
>
> That are the following:
> (a | b) & (a == b) --> a & b
> a | (a == b) --> a | (b ^ 1)
> (a & b) | (a == b)
On Mon, Jul 17, 2023 at 5:34 AM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> This patch adds documentation to wwwdocs to mention the recent introduction
> of Intel new ISA and march.
>
> Ok for trunk?
OK.
> BRs,
> Haochen
>
> ---
> htdocs/gcc-13/changes.html | 4
> htdocs/gcc-14/c
On Mon, Jul 17, 2023 at 2:20 PM Jan Beulich wrote:
>
> On 17.07.2023 08:09, Hongtao Liu wrote:
> > On Fri, Jul 14, 2023 at 5:40 PM Jan Beulich via Gcc-patches
> > wrote:
> >>
> >> Introduce a new alternative permitting all 32 registers to be used as
> >> source without AVX512VL, by broadcasting t
Hi,
> Since this affects the ABI of libgcc I think we don't want that part
> to be user configurable but rather determined by
> some static list of targets that opt-in to this config.
If I do that, do the Linux maintainers want Linux in or out?
> You mention setjmp/longjmp - on darwin and other
Ping.
On Tue, Jul 11, 2023 at 5:16 PM liuhongt via Gcc-patches
wrote:
>
> Similar like we did for CMPXCHG, but extended to all
> ix86_comparison_int_operator since CMPCCXADD set EFLAGS exactly same
> as CMP.
>
> When operand order in CMP insn is same as that in CMPCCXADD,
> CMP insn can be elimin
On Fri, Jul 14, 2023 at 12:28 PM Andreas Schwab wrote:
>
> Why didn't you test that?
Thanks for reporting, and sorry for introducing this warning.
I test all patches before sending them.
In the case of RISC-V backend patches, I build a 2-stage
cross-toolchain and run all regression tests for RV3
> On 17 Jul 2023, at 07:43, FX Coudert wrote:
>
> Hi,
>
>> Since this affects the ABI of libgcc I think we don't want that part
>> to be user configurable but rather determined by
>> some static list of targets that opt-in to this config.
>
> If I do that, do the Linux maintainers want Linux
42 matches
Mail list logo
