GCC 5.2.0 Status Report (2015-07-07), branch frozen

The GCC 5 branch is now frozen for the release of GCC 5.2, all changes require release manager approval from now on. I will shortly announce a first release candidate for GCC 5.2. Previous Report === https://gcc.gnu.org/ml/gcc/2015-06/msg00202.html

[PATCH] Fix PR66739

The following fixes PR66739 - with conditionals not applying a single-use restriction usually causes some regressions. Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk. Richard. 2015-07-07 Richard Biener PR middle-end/66739 * match.pd: Condition A - B ==

[patch, driver] Ignore -ftree-parallelize-loops={0,1}

Hi, currently, we have these spec strings in gcc/gcc.c involving ftree-parallelize-loops: ... %{fopenacc|fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %{fopenacc|fopenmp|ftree-parallelize-loops=*:-pthread}" ... Actually, ftree-parallelize-loops={0,1} means that no para

Re: [RFC] two-phase marking in gt_cleare_cache

On Mon, Jul 6, 2015 at 7:29 PM, Tom de Vries wrote: > On 06/07/15 15:29, Richard Biener wrote: >> >> On Mon, Jul 6, 2015 at 3:25 PM, Richard Biener >> wrote: >>> >>> On Mon, Jul 6, 2015 at 10:57 AM, Tom de Vries >>> wrote: Hi, Using attached untested patch, I managed to minim

Re: flatten cfgloop.h

On Mon, Jul 6, 2015 at 8:11 PM, Jeff Law wrote: > On 07/06/2015 07:38 AM, Michael Matz wrote: >> >> Hi, >> >> On Sun, 5 Jul 2015, Prathamesh Kulkarni wrote: >> >>> Hi, >>> The attached patches flatten cfgloop.h. >>> patch-1.diff moves around prototypes and structures to respective >>> header-files

Re: [Patch,tree-optimization]: Add new path Splitting pass on tree ssa representation

On Sat, Jul 4, 2015 at 2:39 PM, Ajit Kumar Agarwal wrote: > > > -Original Message- > From: Richard Biener [mailto:richard.guent...@gmail.com] > Sent: Tuesday, June 30, 2015 4:42 PM > To: Ajit Kumar Agarwal > Cc: l...@redhat.com; GCC Patches; Vinod Kathail; Shail Aditya Gupta; > Vidhumouli

Re: fix segfault in verify_flow_info() with -dx option

On Tue, Jul 7, 2015 at 2:42 AM, Prathamesh Kulkarni wrote: > On 6 July 2015 at 12:00, Richard Biener wrote: >> On Sun, Jul 5, 2015 at 2:07 PM, Prathamesh Kulkarni >> wrote: >>> Hi, >>> Passing -dx causes segmentation fault: >>> Test case: void f(void) {} >>> >>> ./test.c: In function 'f': >>> ..

Re: [PR25530] Convert (unsigned t / 2) * 2 into (unsigned t & ~1)

On Tue, Jul 7, 2015 at 6:52 AM, Hurugalawadi, Naveen wrote: > Hi, > > Please find attached the patch PR25530.patch that converts the pattern:- > (unsigned / 2) * 2 is into (unsigned & ~1). > > Please review and let me know if its okay. For EXACT_DIV fold-const.c has /* ((T) (X /[ex] C)

Re: [PR25529] Convert (unsigned t * 2)/2 into unsigned (t & 0x7FFFFFFF)

On Tue, Jul 7, 2015 at 8:06 AM, Marc Glisse wrote: > On Tue, 7 Jul 2015, Hurugalawadi, Naveen wrote: > >> Please find attached the patch "PR25529.patch" that converts the pattern:- >> (unsigned * 2)/2 is into unsigned &0x7FFF > > > +/* Simplify (unsigned t * 2)/2 -> unsigned t & 0x7FFF. *

Re: [PR25529] Convert (unsigned t * 2)/2 into unsigned (t & 0x7FFFFFFF)

On Tue, 7 Jul 2015, Richard Biener wrote: On Tue, Jul 7, 2015 at 8:06 AM, Marc Glisse wrote: On Tue, 7 Jul 2015, Hurugalawadi, Naveen wrote: Please find attached the patch "PR25529.patch" that converts the pattern:- (unsigned * 2)/2 is into unsigned &0x7FFF +/* Simplify (unsigned t *

Re: [PR25529] Convert (unsigned t * 2)/2 into unsigned (t & 0x7FFFFFFF)

On Tue, Jul 7, 2015 at 11:24 AM, Marc Glisse wrote: > On Tue, 7 Jul 2015, Richard Biener wrote: > >> On Tue, Jul 7, 2015 at 8:06 AM, Marc Glisse wrote: >>> >>> On Tue, 7 Jul 2015, Hurugalawadi, Naveen wrote: >>> Please find attached the patch "PR25529.patch" that converts the pattern:-

Re: [RFC] two-phase marking in gt_cleare_cache

On 07/07/15 10:42, Richard Biener wrote: On Mon, Jul 6, 2015 at 7:29 PM, Tom de Vries wrote: On 06/07/15 15:29, Richard Biener wrote: On Mon, Jul 6, 2015 at 3:25 PM, Richard Biener wrote: On Mon, Jul 6, 2015 at 10:57 AM, Tom de Vries wrote: Hi, Using attached untested patch, I managed

Re: [RFC] two-phase marking in gt_cleare_cache

On Tue, Jul 7, 2015 at 11:39 AM, Tom de Vries wrote: > On 07/07/15 10:42, Richard Biener wrote: >> >> On Mon, Jul 6, 2015 at 7:29 PM, Tom de Vries >> wrote: >>> >>> On 06/07/15 15:29, Richard Biener wrote: On Mon, Jul 6, 2015 at 3:25 PM, Richard Biener wrote: > >

Re: [gomp] Move openacc vector& worker single handling to RTL

On Mon, Jul 06, 2015 at 03:34:51PM -0400, Nathan Sidwell wrote: > On 07/04/15 16:41, Nathan Sidwell wrote: > >On 07/03/15 19:11, Jakub Jelinek wrote: > > >>If the builtins are not meant to be used by users directly (I assume they > >>aren't) nor have a 1-1 correspondence to a library routine, it i

Re: Clean-ups in match.pd

On Mon, Jul 6, 2015 at 4:08 PM, Richard Biener wrote: > On Sat, Jul 4, 2015 at 4:34 PM, Marc Glisse wrote: >> Hello, >> >> these are just some minor changes. I believe I had already promised a build_ >> function to match integer_each_onep. >> >> Bootstrap+testsuite on powerpc64le-unknown-linux-gn

Re: [PING 3] Re: [PATCH] warn for unsafe calls to __builtin_return_address

On 07/07/2015 04:41 AM, Martin Sebor wrote: > This is a small change to diagnose unsafe calls to > __builtin_{frame,return}_address (with an argument > 2) than > tend to return bogus values or lead to crashes at runtime. > I hadn't realized you went through and implemented the suggestion. Thanks

Re: [PATCH 1/2][ARM] PR/65956 AAPCS update for alignment attribute

Ramana Radhakrishnan wrote: This is OK, the ada testing can go in parallel and we should take this in to not delay rc1 any further. I can confirm, no regressions in check-ada (gcc/testsuite/gnats and gcc/testsuite/acats) following an ada bootstrap on cortex-a15/neon/hard-float. That's the

Re: [PATCH] Do not use floating point registers when compiling with -msoft-float for SPARC

> __builtin_apply* and __builtin_return accesses the floating point registers > on SPARC even when compiling with -msoft-float. Ouch. The fix is OK for all active branches but... > 2015-06-26 Daniel Cederman > > * config/sparc/sparc.c (sparc_function_value_regno_p): Floating >

Re: [PATCH] save takes a single integer (register or 13-bit signed immediate)

> 2015-06-26 Daniel Cederman > > * config/sparc/sparc.md: Window save takes a single integer This will probably break in 64-bit mode, the operand can be a DImode register. -- Eric Botcazou

Re: [PATCH] Update instruction cost for LEON

> 2015-07-03 Daniel Cederman > > * config/sparc/sparc.c (struct processor_costs): Set div cost > for leon to match UT699 and AT697F. Set mul cost for leon3 to > match standard leon3. So UT699 is not a standard LEON3? -- Eric Botcazou

Re: Clean-ups in match.pd

> Bootstrap+testsuite on powerpc64le-unknown-linux-gnu (it looks like > *-match.c takes about 10 minutes to compile in stage2 these days). Yeah, it has already taken back all the speedup brought by the rewrite of the RTL gen* stuff by Richard S. :-( -- Eric Botcazou

[PATCH] MIPS: Fix the call-[1,5,6].c tests to allow the jrc instruction to be matched when testing with microMIPS

Hi, When building the call-[1,5,6].c tests for micromips the jrc rather than the jr instruction is used to call the tail* functions. I have updated the test output to allow the jrc instruction to be matched. I have tested this on the mips-mti-elf target using mips32r2/{-mno-micromips/-mmicromip

Re: Clean-ups in match.pd

On Tue, Jul 7, 2015 at 12:48 PM, Eric Botcazou wrote: >> Bootstrap+testsuite on powerpc64le-unknown-linux-gnu (it looks like >> *-match.c takes about 10 minutes to compile in stage2 these days). > > Yeah, it has already taken back all the speedup brought by the rewrite of the > RTL gen* stuff by R

Re: [Patch, fortran, pr66578, v1] [F2008] Invalid free on allocate(...,source=a(:)) in block

Hi all, hi Paul, Paul thanks for the review. Committed as r225507. Regards, Andre -- Andre Vehreschild * Email: vehre ad gmx dot de Index: gcc/fortran/trans-expr.c === *** gcc/fortran/trans-expr.c (revision 223641) --- gcc

Re: [PATCH] save takes a single integer (register or 13-bit signed immediate)

On 2015-07-07 12:35, Eric Botcazou wrote: 2015-06-26 Daniel Cederman * config/sparc/sparc.md: Window save takes a single integer This will probably break in 64-bit mode, the operand can be a DImode register. You are right, I forgot about that. Is there a mode one can use that

Re: [PATCH] Update instruction cost for LEON

On 2015-07-07 12:37, Eric Botcazou wrote: 2015-07-03 Daniel Cederman * config/sparc/sparc.c (struct processor_costs): Set div cost for leon to match UT699 and AT697F. Set mul cost for leon3 to match standard leon3. So UT699 is not a standard LEON3? LEON3 exists in

Re: [PATCH] Do not use floating point registers when compiling with -msoft-float for SPARC

On 2015-07-07 12:32, Eric Botcazou wrote: ChangeLog must just describe the what, nothing more. If the rationale is not obvious, then a comment must be added _in the code_ itself. * config/sparc/sparc.c (sparc_function_value_regno_p): Do not return true on %f0 for a target with

[PATCH] libgomp: Introduce gomp_thread::spare_team

Try to re-use the previous team to avoid the use of malloc() and free() in the normal case where number of threads is the same. Avoid superfluous destruction and initialization of team synchronization objects. Using the microbenchmark posted here https://gcc.gnu.org/ml/gcc-patches/2008-03/msg009

Re: [PATCH 1/3] [ARM] PR63870 NEON error messages

Alan Lawrence wrote: I note some parts of this duplicate my https://gcc.gnu.org/ml/gcc-patches/2015-01/msg01422.html , which has been pinged a couple of times. Both Charles' patch, and my two, contain parts the other does not... Cheers, Alan Charles Baylis wrote: gcc/ChangeLog: Charles Bayl

[patch committed SH] Fix PR target/66780

The attatched patch reverts a part of the change in r221165 for target/65249. It turned out that that change causes a wrong code problem PR target/66780 which is worse than the ICE with 'R0_REGS' spill failure for a specific program reported by PR65249. I've committed it on trunk and reopened PR ta

[PATCH 0/16][ARM/AArch64] Float16_t support, v2

This is a respin of the series at https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01332.html, plus the two ARM patches on which these depend (https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01333.html). These two somewhat duplicate Charles Baylis' lane-bounds-checking patch at https://gcc.gnu.org/

[PATCH 1/16][ARM] PR/63870 Add qualifier to check lane bounds in expand

As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01333.html (While this falls under PR/63870, and I will link to that in the ChangeLog, it is only a small step towards fixing that PR.) commit 9812db88cff20a505365f68f4065d2fbab998c9c Author: Alan Lawrence Date: Mon Dec 8 11:04:49 2014 +000

[PATCH 4/16][ARM] Add float16x8_t type

Unchanged since https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01336.html commit b9ccac6243415b304024443b74bdc97b3a5954f2 Author: Alan Lawrence Date: Mon Dec 8 18:40:24 2014 + Add float16x8_t + V8HFmode support (regardless of -mfp16-format) diff --git a/gcc/config/arm/arm-builtins.c b/

[PATCH 3/16][ARM] Add float16x4_t intrinsics

As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01335.html commit 54a89a084fbd00e4de036f549ca893b74b8f58fb Author: Alan Lawrence Date: Mon Dec 8 18:40:03 2014 + ARM: float16x4_t intrinsics (v2 - fix v[sg]et_lane_f16 at -O0, no vdup_n/vmov_n) diff --git a/gcc/config/arm/arm_neon.h

[PATCH 2/16][ARM] PR/63870 Add __builtin_arm_lane_check.

As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01334.html commit 1bb1b208a2c8c8b1ee1186c6128a498583fd64fe Author: Alan Lawrence Date: Mon Dec 8 18:36:30 2014 + Add __builtin_arm_lane_check diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 7f5bf87..

[PATCH 6/16][ARM] Remaining float16 intrinsics: vld..., vst..., vget_low/high, vcombine

As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01341.html commit ae6264b144d25fadcbf219e68ddf3d8c5f40be34 Author: Alan Lawrence Date: Thu Dec 11 11:53:59 2014 + ARM 4/4 v2: v(ld|st)[234](q?|_lane|_dup), vcombine, vget_(low|high) (v2 w/ V_uf_sclr) All are tied together wi

[PATCH 5/16][ARM] Add float16x8_t intrinsics

As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01337.html commit 336eb16d3061131fe8d28fad4a473d00768bfe5c Author: Alan Lawrence Date: Tue Dec 9 15:06:38 2014 + ARM float16x8_t intrinsics (v2 - fix v[sg]etq_lane_f16, add vreinterpretq_p16_f16, no vdup_n/lane/vmov_n) diff --git a

[PATCH 7/16][AArch64] Add basic fp16 support

Same as https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01340.html except that two of the tests have been moved into the next patch. (The remaining test is AArch64 only.) gcc/ChangeLog: * config/aarch64/aarch64-builtins.c (aarch64_fp16_type_node): New. (aarch64_init_builtins): Ma

[PATCH 8/16][ARM/AArch64 Testsuite] Add basic fp16 tests

These were originally part of https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01340.html but I have moved into their own subdirectory and adapted them to execute on ARM also (as per https://gcc.gnu.org/ml/gcc-patches/2015-05/msg00656.html) gcc/testsuite/ChangeLog: * gcc.target/aarch64/f

[PATCH 9/16][AArch64] Add support for float16x{4,8}_t vectors/builtins

As https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01341.html commit 49cb53a94a44fcda845c3f6ef11e88f9be458aad Author: Alan Lawrence Date: Tue Dec 2 13:08:15 2014 + AArch64 2/N: Vector/__builtin basics: define+support types, movs, test ABI. Patterns, builtins, intrinsics for {ld1

[PATCH 11/16][AArch64] Implement vcvt_{,high_}f16_f32

This comes from https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01343.html but the other/unrelated intrinsics have moved into the next patch. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_v2sf): Reparameterize to... (aarch64_float_truncate_lo_)

[PATCH 10/16][AArch64] vld{2,3,4}{,_lane,_dup},vcombine,vcreate

As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01342.html commit ef719e5d3d6eccc5cf621851283b7c0ba1a9ee6c Author: Alan Lawrence Date: Tue Aug 5 17:52:28 2014 +0100 AArch64 3/N: v(create|combine|v(ld|st|ld...dup/lane|st...lane)[234](q?))_f16; tests vldN{,_lane,_dup} inc bigendian. Add

[PATCH 12/16][AArch64] vreinterpret(q?), vget_(low|high), vld1(q?)_dup

This is the remainder of https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01343.html combined with https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01344.html, putting together all the intrinsics that didn't require anything outside arm_neon.h. Also update the existing tests in aarch64/. gcc/Change

[PATCH 13/16][AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix

Unchanged since https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01345.html commit 214fcc00475a543a79ed444f9a64061215397cc8 Author: Alan Lawrence Date: Wed Jan 28 13:01:31 2015 + AArch64 6/N: vcvt{,_high}_f32_f16 (using vect_par_cnst_hi_half, fixing bigendian indices) diff --git a/gcc/co

[PATCH 15/16][fold-const.c] Fix bigendian HFmode in native_interpret_real

As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01346.html. Fixes FAIL of advsimd-intrinsics vcreate.c on aarch64_be-none-elf from previous patch. commit e2e7ca148960a82fc88128820f17e7cbd14173cb Author: Alan Lawrence Date: Thu Apr 9 10:54:40 2015 +0100 Fix native_interpret_real for HF

[PATCH 14/16][ARM/AArch64 testsuite] Update advsimd-intrinsics tests to add float16 vectors

This is a respin of https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01347.html, removing many default values of 0x333, to complete that I introduced new macros CHECK_RESULTS{,_NAMED}_NO_FP16 as writing the same list of vector types in four places seemed too many. gcc/testsuite/ChangeLog:

[PATCH 16/16][ARM/AArch64 Testsuite] Add test of vcvt{,_high}_{f16_f32,f32_f16}

This is a respin of https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01349.html . Changes are to: use #if defined(__aarch64__) rather than __ARM_64BIT_STATE__; add an initial call to clean_results; use a different mechanism for adding -mfpu=neon-fp16 on ARM (specifically: we try to add that flag f

[gomp4] libgomp: XFAIL libgomp.oacc-c-c++-common/reduction-4.c for acc_device_nvidia (was: implicit firstprivate and other testcase fixes)

Hi! On Wed, 1 Jul 2015 22:19:01 +0800, Chung-Lin Tang wrote: > This patch "notices" the index variable of an acc loop (internally an OMP_FOR) > inside an OpenACC construct, and completes the implicit firstprivate > behavior as described in the spec. The firstprivate clauses and FIXME in > libgom

RE: [PATCH] MIPS: Fix the call-[1,5,6].c tests to allow the jrc instruction to be matched when testing with microMIPS

> -Original Message- > From: Andrew Bennett [mailto:andrew.benn...@imgtec.com] > Sent: Tuesday, July 07, 2015 6:53 AM > To: gcc-patches@gcc.gnu.org > Cc: Moore, Catherine; Matthew Fortune > Subject: [PATCH] MIPS: Fix the call-[1,5,6].c tests to allow the jrc > instruction > to be matched

Re: [PR66726] Factor conversion out of COND_EXPR

On 07/07/15 07:37, Jeff Law wrote: > On 07/04/2015 06:32 AM, Kugan wrote: > I would also verify that this turns into a MIN_EXPR. I think the patch > as-written won't detect the MIN_EXPR until the _next_ time phi-opt is > called. And one of the benefits we're really looking for here is to > remov

[AArch64][1/2] Mark GOT related MEM rtx as const to help RTL loop IV

Given below testcase, the instruction which load function address from GOT table is not hoisted out of the loop while it should be, as the value is fixed at runtime. The problem is we havn't mark those GOT related mem as READONLY that RTL loop2_iv pass has make conservative decision in check_mayb

[AArch64][2/2] Define TARGET_UNSPEC_MAY_TRAP_P for AArch64

A second patch to improve rtl loop iv on AArch64. We should define this to tell gcc the pattern hidden by these GOT unspec is safe from trap, so gcc could make more positive decision when handling them, for example in RTL loop iv pass, when deciding whether one instruction is invariant candidate,

[gomp4] OpenACC: Complete changes to disallow the independent clause after device_type (was: Remove clause from device_type options)

Hi! On Wed, 1 Jul 2015 07:52:13 -0500, James Norris wrote: > The independent clause is not available for use > with device_type clauses associated with loop > directives. This patch removes the usage. Thanks for noticing this! > Committed to gomp-4_0-branch > --- a/gcc/c/c-parser.c > +++ b/gc

Re: [PATCH 3/16][ARM] Add float16x4_t intrinsics

Hi Alan, On 07/07/15 13:34, Alan Lawrence wrote: As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01335.html For some context, the reference for these is at: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf This patch is ok once you and Charle

[gomp4] OpenACC device_type clause (was: OpenACC: Complete changes to disallow the independent clause after device_type)

Hi Cesar! On Tue, 7 Jul 2015 14:58:20 +0200, I wrote: > On Wed, 1 Jul 2015 07:52:13 -0500, James Norris > wrote: > > The independent clause is not available for use > > with device_type clauses associated with loop > > directives. [...] Independent of this, would you please verify (also for the

[RFCv2] Add steady_clock support to condition_variable

If pthread_cond_timedwaitonclock_np is available in the C library it can be used it to fix part of https://gcc.gnu.org/bugzilla/show_bug.cgi?id=41861 by supporting std::chrono::steady_clock properly with std::condition_variable. This means that code using std::condition_variable::wait_for or std::

RE: [Patch,tree-optimization]: Add new path Splitting pass on tree ssa representation

-Original Message- From: Richard Biener [mailto:richard.guent...@gmail.com] Sent: Tuesday, July 07, 2015 2:21 PM To: Ajit Kumar Agarwal Cc: l...@redhat.com; GCC Patches; Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida; Nagaraju Mekala Subject: Re: [Patch,tree-optimization]: Add

[gomp4] libgomp: Remove C-only XFAILs added in "Tune XFAILs" (was: openacc id builtin)

Hi! On Fri, 26 Jun 2015 08:39:41 -0400, Nathan Sidwell wrote: > I discovered a latent bug in the openacc thread id builtin and associated > unspec. They should not be treated as constant functions, because that > causes > the compiler to consider them constant across threads. Which of course

[patch 0/9] Flattening and initial module rebuilding

This is a series of 9 patches which does some flattening, some module building, and some basic cleanups. I am presenting them as 9 patches for easier review. The latter couple of patches affect a lot of the same files that follow on patches then adjust, I've decided NOT to put the automated c

[patch 1/9] header additions and aggregators

This patch implements most of the core concepts described in my previous email (https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01846.html) It goes into detail of the analysis which resulted in this layout. Most of the unnecessary prerequisites have been removed, so we can start introducing bac

[patch 2/9] flatten regset.h

This patch flattens regset.h. it only includes bitmap.h which will come from backend.h and hard-reg-set.h which is going to be included by rtl.h. The vast majority of files which include regset already include rtl.h, so its almost never needed. This patch shows the result on all files in a v

[patch 3/9] Flatten lra-int.h

This patch flattens lra-int.h. It currently clumps 7 includes, which no file needs more than 4. Flatten it here and find a better aggregator for rtl related files later. Bootstraps from scratch on x86_64-unknown-linux-gnu with no new regressions. Also compiles all the files in config-list.mk

[patch 5/9] Flatten ira-int.h

Flatten ira-int.h, yet another header that includes cfgloop.h. Most of the includes from here do actually make it into the source files, so once the include reduction is completed and we see if they are actually needed, some may go back in. Bootstraps from scratch on x86_64-unknown-linux-gnu

[patch 6/9] Flatten gimple-streamer.h

This one is amusing... 3 header files, all of them already included in all the files which include this. Bootstraps from scratch on x86_64-unknown-linux-gnu with no new regressions. Also compiles all the files in config-list.mk. * gimple-streamer.h: Remove all includes. Index: gimple-stre

[patch 7/9] Flatten cfgloop.h

This patch flattens cfgloop.h. cfgloopmanip.h is utilized by numerous files which include cfgloop.h, so it seems to make sense to leave it here. The other 3 header files are going to form part of backend.h, so take them out. I didn't bother posting the changes to all the source files since a

[patch 8/9] Flatten df.h

This patch fixes up df.h. It contains 5 headers that will form part of backend.has well as hard-reg-set.h which is now going to be included by rtl.h. The other 3 includes are required for df.h to compile, and it makes sense to leave them here. furthermore, resource.h, sched-int.h and valtrac

[patch 4/9] Flatten sel-sched-dump.h and sel-sched-ir.h

This patch flattens both sel-sched-dump.h and sel-sched-ir.h. Both these files end up including cfgloop.h, so in preparation for flattening cfgloop.h, flatten these. Note they actually have only a small effect on what includes them. Bootstraps from scratch on x86_64-unknown-linux-gnu with no

Re: [PATCH] Simple optimization for MASK_STORE.

Hi Richard, Did you have a chance to look at this updated patch? Thanks. Yuri. 2015-06-18 17:32 GMT+03:00 Yuri Rumyantsev : > Richard, > > Here is updated patch which does not include your proposal related to > the target hook deletion. > You wrote: >> I still don't understand why you need the n

Re: [RFC] two-phase marking in gt_cleare_cache

Hi, On Mon, 6 Jul 2015, Richard Biener wrote: > >> By doing so, we make the behaviour of gt_cleare_cache independent of the > >> order in which the entries are visited, turning: > >> - hard-to-trigger bugs which trigger for one visiting order but not for > >> another, into > >> - more easily tr

Re: [patch 4/9] Flatten sel-sched-dump.h and sel-sched-ir.h

On Tue, 7 Jul 2015, Andrew MacLeod wrote: > This patch flattens both sel-sched-dump.h and sel-sched-ir.h. Both these files > end up including cfgloop.h, so in preparation for flattening cfgloop.h, > flatten these. Note they actually have only a small effect on what includes > them. This patch re

Re: [gomp4] Allow parameter declarations with deviceptr

Hi! On Wed, 1 Jul 2015 16:33:24 -0700, Cesar Philippidis wrote: > On 07/01/2015 02:25 PM, James Norris wrote: > > > This patch allows parameter declarations to be used as > > arguments to deviceptr for C and C++. Thanks! I suppose this does fix ? > Does this fix a

RE: [PATCH] MIPS: Fix the call-[1,5,6].c tests to allow the jrc instruction to be matched when testing with microMIPS

> OK. Committed as SVN 225516. Regards, Andrew

Re: [patch 4/9] Flatten sel-sched-dump.h and sel-sched-ir.h

On 07/07/2015 10:01 AM, Alexander Monakov wrote: On Tue, 7 Jul 2015, Andrew MacLeod wrote: This patch flattens both sel-sched-dump.h and sel-sched-ir.h. Both these files end up including cfgloop.h, so in preparation for flattening cfgloop.h, flatten these. Note they actually have only a small

[PATCH][13/n] Remove GENERIC stmt combining from SCCVN

This moves a few more patterns that show up during bootstrap. Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk. Richard. 2015-07-07 Richard Biener * fold-const.c (fold_binary_loc): Move (X & C2) << C1 -> (X << C1) & (C2 << C1) simplification ...

Re: [gomp] Move openacc vector& worker single handling to RTL

On 07/07/15 05:54, Jakub Jelinek wrote: On Mon, Jul 06, 2015 at 03:34:51PM -0400, Nathan Sidwell wrote: How does this interact with #pragma acc routine {gang,worker,vector,seq} ? Or is that something to be added later on? That is to be added later on. I suspect such routines will trivially

[Patch,microblaze]: Optimized Instruction prefetch with the generation of wic

All: Please find the patch for optimized usage of instruction prefetch with the generation of microblaze instruction "wic". No regressions is seen in Deja GNU tests for microblaze. [Patch,microblaze]: Optimized Instruction prefetch with the generation of wic instruction. The change

Re: [gomp] Move openacc vector& worker single handling to RTL

On Tue, Jul 07, 2015 at 10:12:56AM -0400, Nathan Sidwell wrote: > On 07/07/15 05:54, Jakub Jelinek wrote: > >On Mon, Jul 06, 2015 at 03:34:51PM -0400, Nathan Sidwell wrote: > > >How does this interact with > >#pragma acc routine {gang,worker,vector,seq} ? > >Or is that something to be added later

Re: [PR66726] Factor conversion out of COND_EXPR

On 07/07/2015 06:50 AM, Kugan wrote: Thanks for the review. I have addressed your comments above in the attached patch. I have one question with respect to unary operation. For generic unary operation with INTEGER_CST, do we skip this or do we have to perform the inverse operation so that the c

Re: [gomp] Move openacc vector& worker single handling to RTL

On 07/07/15 10:22, Jakub Jelinek wrote: On Tue, Jul 07, 2015 at 10:12:56AM -0400, Nathan Sidwell wrote: Wouldn't function attributes be better for that case, and just use the internal functions for the case when the mode is being changed in the middle of function? It may be. I've been think

[PATCH] libstdc++-v3/fragment.am (AM_CPPFLAGS): Add CPPFLAGS

Hi build machinery maintainers, when the host system does not have the iconv-devel package installed, but the target-prefix does contain iconv.h, in libstdc++/include the creation of the precompiled headers fails with " not found". While libstdc++/configure detects INCICONV="-I$target_prefix/incl

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On 06/29/2015 07:15 PM, Jim Wilson wrote: This is my suggested fix for PR 65932, which is a linux kernel miscompile with gcc-5.1. The problem here is caused by a chain of events. The first is that the relatively new eipa_sra pass creates fake parameters that behave slightly differently than nor

[gomp4] Handle deviceptr from an outer directive

Hi, This patch fixes an issue where the deviceptr clause in an outer directive was being ignored during implicit variable definition on a nested directive. Committed to gomp-4_0-branch. Jim diff --git a/gcc/gimplify.c b/gcc/gimplify.c index 51aadc0..a721a52 100644 --- a/gcc/gimplify.c +++ b/gcc

Re: RE: [Ping^3] [PATCH, ARM, libgcc] New aeabi_idiv function for armv6-m

Ping! On 30/04/15 10:40, Hale Wang wrote: -Original Message- From: Hale Wang [mailto:hale.w...@arm.com] Sent: Monday, February 09, 2015 9:54 AM To: Richard Earnshaw Cc: Hale Wang; gcc-patches; Matthew Gretton-Dann Subject: RE: [Ping^2] [PATCH, ARM, libgcc] New aeabi_idiv function for arm

Re: [PING][PATCH, 1/2] Merge rewrite_virtuals_into_loop_closed_ssa from gomp4 branch

On 06/07/15 15:44, Richard Biener wrote: On Mon, 6 Jul 2015, Tom de Vries wrote: On 25/06/15 09:42, Tom de Vries wrote: Hi, this patch merges rewrite_virtuals_into_loop_closed_ssa (originally submitted here: https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01236.html ) to trunk. Bootstrapped an

RE: [PATCH] MIPS: Do not generate micromips code for the no-smartmips-lwxs.c testcase

> Hi Andrew, > > Instead of adding the -mno-micromips option to dg-options, please change the > MIPS16 attribute to NOCOMPRESSION. > > Index: gcc.target/mips/no-smartmips-lwxs.c > === > --- gcc.target/mips/no-smartmips-lwxs.c (revisi

RE: [PATCH] MIPS: fix failing branch range checks for micromips

> I see that you are naming these tests after the original branch- tests > that they were derived from. > I think it would be better to keep all of the microMIPS tests named umips-???. > I don't think preserving the original number is important. I have named the microMIPS tests umips-branch-??? to

RE: [PATCH] MIPS: Update stack-1.c testcase to match micromips jraddiusp instruction.

> > I'm not sure this is the right approach here. If we get a jraddiusp then the > > problem that the test is trying to cover can't possibly happen anyway. > > (The test is checking if a load and final stack adjustment are ever re- > ordered > > from what I can see.) > > > > I'd just mark the test

Re: [PATCH 3/16][ARM] Add float16x4_t intrinsics

On 07/07/15 14:09, Kyrill Tkachov wrote: Hi Alan, On 07/07/15 13:34, Alan Lawrence wrote: As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01335.html For some context, the reference for these is at: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Tue, Jul 7, 2015 at 8:07 AM, Jeff Law wrote: > On 06/29/2015 07:15 PM, Jim Wilson wrote: > So if these "copies" require a conversion, then isn't it fundamentally > wrong to have a PHI node which copies between them? That would seem to > implicate the eipa_sra pass as needing to be aware of th

Re: [PATCH 3/16][ARM] Add float16x4_t intrinsics

Kyrill Tkachov wrote: On 07/07/15 14:09, Kyrill Tkachov wrote: Hi Alan, On 07/07/15 13:34, Alan Lawrence wrote: As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01335.html For some context, the reference for these is at: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_a

Tests for libgomp based on OpenMP Examples 4.0.2.

With this letter I propose a patch with tests for libgomp based on OpenMP Examples 4.0.2 both for C and Fortran. The changes are: Renamed existing tests based on OpenMP Examples to make the names more clear. Added 16 tests for simd construct and 10 for depend clause. - Since

Re: [PATCH] save takes a single integer (register or 13-bit signed immediate)

> You are right, I forgot about that. Is there a mode one can use that > changes depending on the target architecture (32-bit on 32-bit > architectures and 64-bit on 64-bit architectures)? Yes, Pmode does exactly that, but you cannot use it directly in the MD file. > Or does one have to add a 32-

Re: [PATCH 3/16][ARM] Add float16x4_t intrinsics

On 07/07/15 17:34, Alan Lawrence wrote: Kyrill Tkachov wrote: On 07/07/15 14:09, Kyrill Tkachov wrote: Hi Alan, On 07/07/15 13:34, Alan Lawrence wrote: As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01335.html For some context, the reference for these is at: http://infocenter.arm.com/

Re: Tests for libgomp based on OpenMP Examples 4.0.2.

Comment on the patch: simd-5.f90 file is marked as xfail since the test fails because 'simd collapse' is an unsupported combination for Fortran (which though is valid in OpenMP API). 2015-07-07 19:48 GMT+03:00 Maxim Blumental : > With this letter I propose a patch with tests for libgomp based on

Re: [PATCH 3/16][ARM] Add float16x4_t intrinsics

Kyrill Tkachov wrote: On 07/07/15 17:34, Alan Lawrence wrote: Kyrill Tkachov wrote: On 07/07/15 14:09, Kyrill Tkachov wrote: Hi Alan, On 07/07/15 13:34, Alan Lawrence wrote: As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01335.html For some context, the reference for these is at: http

Re: [Ping^3] [PATCH, ARM, libgcc] New aeabi_idiv function for armv6-m

On 07/07/15 16:23, Tejas Belagod wrote: > Ping! > I've had a look at this (sorry for the delay). I think it's mostly OK, but I have two comments to make. 1) It's quite hard to understand the algorithm and there are no comments to aid understanding (to be fair, there aren't many comments on the

RE: [PATCH] MIPS: Update stack-1.c testcase to match micromips jraddiusp instruction.

> -Original Message- > From: Andrew Bennett [mailto:andrew.benn...@imgtec.com] > Sent: Tuesday, July 07, 2015 12:14 PM > To: Moore, Catherine; Matthew Fortune; gcc-patches@gcc.gnu.org > Subject: RE: [PATCH] MIPS: Update stack-1.c testcase to match micromips > jraddiusp instruction. > > >

Re: Tests for libgomp based on OpenMP Examples 4.0.2.

On Tue, Jul 07, 2015 at 08:08:16PM +0300, Maxim Blumental wrote: > Comment on the patch: > > simd-5.f90 file is marked as xfail since the test fails because 'simd > collapse' is an unsupported combination for Fortran (which though is > valid in OpenMP API). I'll have a look, that is supposed to w

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Thu, Jul 2, 2015 at 2:07 AM, Richard Earnshaw wrote: > Not quite, ARM state still has more flexible addressing modes for > unsigned byte loads than for signed byte loads. It's even worse with > thumb1 where some signed loads have no single-register addressing mode > (ie you have to copy zero i

Re: Tests for libgomp based on OpenMP Examples 4.0.2.

On Tue, Jul 07, 2015 at 20:17:48 +0200, Jakub Jelinek wrote: > On Tue, Jul 07, 2015 at 08:08:16PM +0300, Maxim Blumental wrote: > > > Added 16 tests for simd construct and 10 for depend clause. > > Any new tests that aren't in Examples 4.0.* document should go one level > higher, to libgomp.{c,c++

  1   2   >