On 12/01/15 20:15, Philipp Tomsich wrote:
---
gcc/ChangeLog-2014| 10 ++
gcc/config/arm/arm-cores.def | 1 +
gcc/config/arm/arm-tables.opt | 3 +++
gcc/config/arm/arm-tune.md| 3 ++-
gcc/config/arm/arm.c | 22 ++
gcc/config/arm/arm
On 12/01/15 20:15, Philipp Tomsich wrote:
---
gcc/config/aarch64/aarch64.md | 2 +-
gcc/config/arm/types.md | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 1f6b1b6..98f4f30 100644
--- a/gcc/confi
On 09/01/2015 19:22, Kyrill Tkachov wrote:
Hi Xingxing,
On 19/12/14 11:01, Xingxing Pan wrote:
+/* Return true if vector element size is byte. */
Minor nit: two spaces after full stop and before */ Same in other places
in the patch.
+bool
+marvell_whitney_vector_element_size_is_byte (rtx ins
On Sun, Jan 11, 2015 at 9:55 PM, Andreas Tobler wrote:
> Hi,
>
> I have here a possible way to make the enum_9.f90 and the enum_10.f90 work
> under arm*-*-freebsd*. The solution for enum_9.f90 is straight forward. But
> the one for enum_10.f90 requires a reordering of the dg-additional-sources
> l
On 19/11/14 02:43, Joey Ye wrote:
Current thumb2 -Os generates suboptimal code for following tail call case:
int f4(int b, int a, int c, int d);
int g(int a, int b, int c, int d)
{ return f4(b, a, c, d); }
arm-none-eabi-gcc -Os -mthumb -mcpu=cortex-m3 test.c
push
{r4, lr}
mov r4, r1
mov r1,
On Mon, Jan 12, 2015 at 11:12 PM, Jeff Law wrote:
> On 04/08/14 14:07, Mike Stump wrote:
>>
>> Something broke in the compiler to cause combine to incorrectly optimize:
>>
>> (insn 12 11 13 3 (set (reg:SI 604 [ D.6102 ])
>> (lshiftrt:SI (subreg/s/u:SI (reg/v:DI 601 [ x ]) 0)
>>
On Mon, 12 Jan 2015, Thomas Preud'homme wrote:
> Hi all,
>
> To identify if a set of loads, shift, cast, mask (bitwise and) and bitwise OR
> is equivalent to a load or byteswap, the bswap pass assign a number to each
> byte loaded according to its significance (1 for lsb, 2 for next least
> si
On Sun, 11 Jan 2015, Prathamesh Kulkarni wrote:
> Hi,
> This is a revamped expr.h flattening flattening patch rebased on
> tree.h and tree-core.h flattening patch (r219402).
> It depends upon the following patch to get committed.
> https://gcc.gnu.org/ml/gcc-patches/2015-01/msg00565.html
>
> Chan
On Thu, Jan 8, 2015 at 8:51 PM, Andreas Tobler wrote:
> On 08.01.15 17:27, Richard Earnshaw wrote:
>>
>> On 29/12/14 18:44, Andreas Tobler wrote:
>>>
>>> All,
>>>
>>> here is the third attempt to support ARM with FreeBSD.
>>>
>>> In the meantime we found another issue in the unwinder where I had t
On 13 January 2015 at 15:34, Richard Biener wrote:
> On Sun, 11 Jan 2015, Prathamesh Kulkarni wrote:
>
>> Hi,
>> This is a revamped expr.h flattening flattening patch rebased on
>> tree.h and tree-core.h flattening patch (r219402).
>> It depends upon the following patch to get committed.
>> https:
On 9 January 2015 at 16:31, Tejas Belagod wrote:
> gcc/testsuite:
>
> * gcc.target/aarch64/vect-movi.c: Check for vectorization for
> 64-bit and 128-bit.
OK /Marcus
Several sub-based patterns allowed the stack pointer to be the destination
but not the first source. This looked like an oversight; in all the patterns
changed here (but not for example in *sub_mul_imm_), the instruction
allows the stack pointer to appear in both positions.
Tested on aarch64-linu
Hi!
On Mon, 12 Jan 2015 17:39:16 +0100, Jakub Jelinek wrote:
> On Mon, Jan 12, 2015 at 05:32:14PM +0100, Thomas Schwinge wrote:
> > I have now committed the patch to gomp-4_0-branch in the following form.
> > The issues raised above remain to be resolved.
(I'll try to address those later on.)
On 7 January 2015 at 14:01, Renlin Li wrote:
> Is it Okay for branch 4.9?
>
> gcc/ChangeLog:
>
> 2014-11-19 Renlin Li
> PR target/63424
> * config/aarch64/aarch64-simd.md (v2di3): New.
>
> gcc/testsuite/ChangeLog:
>
> 2014-11-19 Renlin Li
> PR target/63424
> * gcc.target/aarch64
Jeff Law writes:
> For "fun" I've got an m68k bootstrap of the trunk running. I don't expect
> it to finish for at least a week or so, assuming it runs to completion.
The last time I did that it took about 10 days (with all languages
enabled, running in Aranym on a moderately fast host).
Andre
Hi Paul,
thanks for the reviewed and the valued comments.
Just for completeness I have attached the patch with the changes requested.
Bootstraps and regtests ok on x86_64-linux-gnu.
Regards,
Andre
On Mon, 12 Jan 2015 22:07:29 +0100
Paul Richard Thomas wrote:
> Hi Andre,
>
> +
On Mon, Jan 12, 2015 at 12:19 PM, Jakub Jelinek wrote:
> Hi!
>
> The 991213-3.c testcase ICEs on aarch64-linux with -mabi=ilp32
> since wide-int merge. The problem is that
> x = convert_memory_address (Pmode, x)
> is used twice on a VOIDmode CONST_INT, which is wrong.
> For non-VOIDmode rtl the s
On 10 December 2014 at 02:18, Andrew Pinski wrote:
> Hi,
> As mentioned in
> https://gcc.gnu.org/ml/gcc-patches/2014-12/msg00609.html, the
> load/store pair peepholes currently accept volatile mem which can
> cause wrong code as the architecture does not define which part of the
> pair happens f
On 13 January 2015 at 10:47, Richard Sandiford
wrote:
> Several sub-based patterns allowed the stack pointer to be the destination
> but not the first source. This looked like an oversight; in all the patterns
> changed here (but not for example in *sub_mul_imm_), the instruction
> allows the sta
On 13 January 2015 at 04:48, Andrew Pinski wrote:
> ChangeLog:
> * config/aarch64/aarch64.c (fusion_load_store): Check dest mode
> instead of src mode.
>
>
> * gcc.target/aarch64/store-pair-1.c: New testcase.
OK, thanks /Marcus
On Mon, 12 Jan 2015, Richard Biener wrote:
>
> I am testing the following patch to fix a latent bug in the vectorizer
> dealing with redundant DRs.
>
> Bootstrap and regtest pending on x86_64-unknown-linux-gnu.
Which shows the patch is bogus. Instead we are not prepared to
handle this situatio
On Mon, Jan 12, 2015 at 03:04:20PM -0700, Jeff Law wrote:
> On 01/12/15 14:51, Magnus Granberg wrote:
> >måndag 12 januari 2015 12.11.17 skrev H.J. Lu:
> >>On Mon, Jan 12, 2015 at 12:03 PM, Jeff Law wrote:
> >>>On 01/12/15 12:59, H.J. Lu wrote:
> I don't know if -pg will work PIE on any targe
On Mon, Jan 12, 2015 at 03:04:20PM -0700, Jeff Law wrote:
> On 01/12/15 14:51, Magnus Granberg wrote:
> >måndag 12 januari 2015 12.11.17 skrev H.J. Lu:
> >>On Mon, Jan 12, 2015 at 12:03 PM, Jeff Law wrote:
> >>>On 01/12/15 12:59, H.J. Lu wrote:
> I don't know if -pg will work PIE on any targe
On Mon, Jan 12, 2015 at 11:50:41PM +, Joseph Myers wrote:
> On Mon, 12 Jan 2015, H.J. Lu wrote:
>
> > +if test x$enable_default_pie = xyes; then
> > + AC_MSG_CHECKING(if $target supports default PIE)
> > + enable_default_pie=no
> > + case $target in
> > +i?86*-*-linux* | x86_64*-*-linux
Hi,
is this patch commited now? I don't have the rights to do so myself.
- Andre
On Sun, 28 Dec 2014 17:17:50 +0100
FX wrote:
>
> > 2014-12-28 Andre Vehreschild
> >
> >* trans-decl.c (gfc_finish_var_decl): Fixed displaced comment.
> >* trans-stmt.c (gfc_trans_allocate): Fixed inde
On Tue, Jan 13, 2015 at 04:54:32AM -0800, H.J. Lu wrote:
> On Mon, Jan 12, 2015 at 03:04:20PM -0700, Jeff Law wrote:
> > On 01/12/15 14:51, Magnus Granberg wrote:
> > >måndag 12 januari 2015 12.11.17 skrev H.J. Lu:
> > >>On Mon, Jan 12, 2015 at 12:03 PM, Jeff Law wrote:
> > >>>On 01/12/15 12:59,
The following removes -fvar-tracking-assignments from being eligible
to the optimization attribute/pragma which fixes LTO operation for
mixed inputs (LTO just drops debug stmts if the flag is false).
In theory we could also fix inlining to do that when inlining
debug stmts into a non-VTA function
The following patch guards LTO against PARM_DECLs without DECL_CONTEXT.
Bootstrapped on x86_64-unknown-linux-gnu, testing in progress.
Richard.
2015-02-13 Richard Biener
PR lto/64373
* lto-streamer-out.c (tree_is_indexable): Guard for NULL
DECL_CONTEXT.
* gc
When a optimization pass in the loop pipeline moves stmts between
loops or removes loops we have to reset the SCEV cache to not
have stale CHREC_LOOPs. This patch does it for loop distribution
for which I have a testcase.
Bootstrapped on x86_64-unknown-linux-gnu, testing in progress.
Richard.
On Tue, Jan 13, 2015 at 02:04:26PM +0100, Richard Biener wrote:
> The following removes -fvar-tracking-assignments from being eligible
> to the optimization attribute/pragma which fixes LTO operation for
> mixed inputs (LTO just drops debug stmts if the flag is false).
>
> In theory we could also
The following fixes a bug in outer loop reduction vectorization which
happens to use a bogus vectorized stmt for the inner loop exit PHI.
Bootstrap and regtest in progress on x86_64-unknown-linux-gnu.
Richard.
2015-01-13 Richard Biener
PR tree-optimization/64493
PR tree-opti
On 12 January 2015 at 20:15, Philipp Tomsich
wrote:
> +2014-11-19 Philipp Tomsich
> +
> + * config/aarch64/aarch64-cores.def (xgene1): Update/add the
> + xgene1 (APM XGene-1) core definition.
> + * gcc/config/aarch64/aarch64.c: Add cost tables for APM XGene-1
> + * conf
Hello,
The LRA register alloator is enabled by default for the ARM backend and
-mno-lra should no longer be used. This patch removes the -mlra/-mno-lra
option from the ARM backend.
arm-none-linux-gnueabihf passes gcc-check with no new failures.
Matthew
2015-01-13 Matthew Wahab
P
On Tue, 13 Jan 2015, Jakub Jelinek wrote:
> On Tue, Jan 13, 2015 at 02:04:26PM +0100, Richard Biener wrote:
> > The following removes -fvar-tracking-assignments from being eligible
> > to the optimization attribute/pragma which fixes LTO operation for
> > mixed inputs (LTO just drops debug stmts i
On Tue, Jan 13, 2015 at 02:26:39PM +0100, Richard Biener wrote:
> The following seems to work (for the testcase). Testing coverage
> of this mode will of course be bad.
LGTM.
> 2015-01-13 Richard Biener
>
> PR lto/64415
> * tree-inline.c (insert_debug_decl_map): Check destination
On 12 January 2015 at 20:15, Philipp Tomsich
wrote:
> ---
> gcc/config/aarch64/aarch64.md | 1 +
> gcc/config/arm/xgene1.md | 531
> ++
> 2 files changed, 532 insertions(+)
> create mode 100644 gcc/config/arm/xgene1.md
>
> diff --git a/gcc/config/a
On 13/01/15 13:46, Marcus Shawcroft wrote:
> On 12 January 2015 at 20:15, Philipp Tomsich
> wrote:
>> ---
>> gcc/config/aarch64/aarch64.md | 1 +
>> gcc/config/arm/xgene1.md | 531
>> ++
>> 2 files changed, 532 insertions(+)
>> create mode 100644 g
On 11 January 2015 at 02:37, Andrew Pinski wrote:
> On Tue, Nov 11, 2014 at 6:47 AM, Marcus Shawcroft
> wrote:
>> On 30 October 2014 08:54, Gopalasubramanian, Ganesh
>> wrote:
>>
>>> 2014-10-30 Ganesh Gopalasubramanian
>>
>> Check the whitespace in your ChangeLog line.
>>
>>> * config/
On Tue, Jan 13, 2015 at 6:13 AM, Marcus Shawcroft
wrote:
> On 11 January 2015 at 02:37, Andrew Pinski wrote:
>> On Tue, Nov 11, 2014 at 6:47 AM, Marcus Shawcroft
>> wrote:
>>> On 30 October 2014 08:54, Gopalasubramanian, Ganesh
>>> wrote:
>>>
2014-10-30 Ganesh Gopalasubramanian
>>>
>>> C
On Mon, Jan 12, 2015 at 03:04:20PM -0700, Jeff Law wrote:
> On 01/12/15 14:51, Magnus Granberg wrote:
> >måndag 12 januari 2015 12.11.17 skrev H.J. Lu:
> >>On Mon, Jan 12, 2015 at 12:03 PM, Jeff Law wrote:
> >>>On 01/12/15 12:59, H.J. Lu wrote:
> I don't know if -pg will work PIE on any targe
Great. I should have an update patch-set ready & tested later tonight.
Best,
Phil.
> On 13 Jan 2015, at 15:18, Andrew Pinski wrote:
>
> On Tue, Jan 13, 2015 at 6:13 AM, Marcus Shawcroft
> wrote:
>> On 11 January 2015 at 02:37, Andrew Pinski wrote:
>>> On Tue, Nov 11, 2014 at 6:47 AM, Marcus S
Lengthy discussion : https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59448
Basically we can generate incorrect code for an atomic consume operation
in some circumstances. The general feeling seems to be that we should
simply promote all consume operations to an acquire operation until
there is a
The existing tests for these functions are compile-only so didn't
catch that I forgot to export these new symbols. I'll add a better
test next week.
Tested x86_64-linux, committed to trunk.
commit d428e75af04d995451a917ef7c9caed6b8cee737
Author: Jonathan Wakely
Date: Tue Jan 13 14:27:34 2015 +
On Tue, Jan 13, 2015 at 3:56 PM, Andrew MacLeod wrote:
> Lengthy discussion : https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59448
>
> Basically we can generate incorrect code for an atomic consume operation in
> some circumstances. The general feeling seems to be that we should simply
> promote al
On Mon, Jan 12, 2015 at 6:52 PM, Pat Haugen wrote:
> Following backport tested on 4.8/4.9 with no new regressions. Ok to commit
> to those branches?
>
> -Pat
>
>
> 2015-01-12 Pat Haugen
>
> Backport from mainline
> 2014-12-20 Segher Boessenkool
>
>
> PR target/64358
>
On 01/13/2015 09:59 AM, Richard Biener wrote:
On Tue, Jan 13, 2015 at 3:56 PM, Andrew MacLeod wrote:
Lengthy discussion : https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59448
Basically we can generate incorrect code for an atomic consume operation in
some circumstances. The general feeling seem
__set_neon_cumulative_sat() modifies the contents on the QC flag, and
some intrinsics do so too: this patch adds the explicit dependency on
the asm statement, to avoid code reordering or removal.
When writing QC, the asm statement now has a fake input dependency,
which is the output of the intrins
* gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vhadd.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vhsub.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmax.c: New file.
* gcc.target/
* gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
new file mode 100644
index 000..168cf5e
--- /dev/null
+++ b/gcc/testsuite/gcc.t
This patch series is a follow-up of the conversion of my existing
testsuite into DejaGnu. It does not yet cover all the tests I wrote,
but I chose to post this set to have a chance to have it accepted
before stage 4. I will have 35 more files to convert after this set.
Most of the patches only add
* gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
new file mode 100644
index 000..53cd8f3
--- /dev/null
+++ b/gcc/testsuite/gcc.tar
* gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc
* gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlal.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc
b/gcc/testsuite/gcc
* gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file.
* gcc.target/a
* gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc
b/gcc/tests
* gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc
b/
* gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmla_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmls_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc
b/gcc/testsuite
* gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc
b/gcc/tests
* gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c: New file.
diff --git
a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_
* gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc
b/g
* gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubl.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddl.c: Use code from
vXXXl.inc.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.i
* gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsli_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsri_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc
b/gcc/testsuite
* gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vpadd.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vpmax.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vpmin.c: New file.
diff --git a/gcc/testsuite/g
* gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubw.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddw.c: Use code from
vXXXw.inc.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.i
* gcc.target/aarch64/advsimd-intrinsics/vmovl.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
new file mode 100644
index 000..427c9ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch6
* gcc.target/aarch64/advsimd-intrinsics/vmovn.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c
new file mode 100644
index 000..bc2c2ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch6
* gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c
new file mode 100644
index 000..978cd9b
--- /dev/null
+++ b/gcc/testsuite/gcc.t
* gcc.target/aarch64/advsimd-intrinsics/vmul_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c
new file mode 100644
index 000..be0ee65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aar
* gcc.target/aarch64/advsimd-intrinsics/vmull.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c
new file mode 100644
index 000..3fdd51e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch6
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (CHECK):
Add trace.
(CHECK_FP): Likewise.
(CHECK_CUMULATIVE_SAT): Likewise.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
* gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c
new file mode 100644
index 000..d3aa879
--- /dev/null
+++ b/gcc/testsuite/gc
* gcc.target/aarch64/advsimd-intrinsics/vpaddl.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddl.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddl.c
new file mode 100644
index 000..779cc77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aar
* gcc.target/aarch64/advsimd-intrinsics/vmvn.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c
new file mode 100644
index 000..04bb5f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/a
* gcc.target/aarch64/advsimd-intrinsics/vqdmulh_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_lane.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_lane.c
new file mode 100644
index 000..5260676
--- /dev/null
+++ b/gcc/testsu
* gcc.target/aarch64/advsimd-intrinsics/vqdmulh_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_n.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_n.c
new file mode 100644
index 000..ab66e2d
--- /dev/null
+++ b/gcc/testsuite/gcc.t
* gcc.target/aarch64/advsimd-intrinsics/vpadal.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadal.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadal.c
new file mode 100644
index 000..dcedb45
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aar
* gcc.target/aarch64/advsimd-intrinsics/vqdmulh.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh.c
new file mode 100644
index 000..8d2a365
--- /dev/null
+++ b/gcc/testsuite/gcc.target/
* gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c
new file mode 100644
index 000..9e73009
--- /dev/null
+++ b/gcc/testsuite/gcc.t
* gcc.target/aarch64/advsimd-intrinsics/vqdmull.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull.c
new file mode 100644
index 000..e71a624
--- /dev/null
+++ b/gcc/testsuite/gcc.target/
* gcc.target/aarch64/advsimd-intrinsics/vqdmull_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_lane.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_lane.c
new file mode 100644
index 000..12f2a6b
--- /dev/null
+++ b/gcc/testsu
On Tue, 2015-01-13 at 09:56 -0500, Andrew MacLeod wrote:
> The problem with the patch in the PR is the memory model is immediately
> promoted from consume to acquire. This happens *before* any of the
> memmodel checks are made. If a consume is illegally specified (such as
> in a compare_exch
* gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vtrn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Use code from
vshuffle.inc.
* gcc.target/aarch64/advsimd-intrinsics/vzip.c: Use code fro
* gcc.target/aarch64/advsimd-intrinsics/vmlX.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmla.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmls.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX.inc
b/gcc/testsuite/gcc.ta
On 01/12/2015 09:38 PM, Kaz Kojima wrote:
> 2015-01-13 Kaz Kojima
>
> * configure.host: Remove extra brackets for sh.
Ok, thanks.
r~
On 01/13/2015 10:20 AM, Torvald Riegel wrote:
On Tue, 2015-01-13 at 09:56 -0500, Andrew MacLeod wrote:
The problem with the patch in the PR is the memory model is immediately
promoted from consume to acquire. This happens *before* any of the
memmodel checks are made. If a consume is illegall
On Mon, Jan 12, 2015 at 5:13 PM, Richard Henderson wrote:
> On 01/12/2015 04:57 PM, H.J. Lu wrote:
>> The problem is my x86_64-*-linux-gnux32 patch
>>
>> https://gcc.gnu.org/ml/gcc-patches/2012-08/msg01083.html
>>
>> was never accepted upstream. Can I apply it to config.guess
>> in GCC?
>
> Ah.
* gcc.target/aarch64/advsimd-intrinsics/vmull_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_n.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_n.c
new file mode 100644
index 000..df28a94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/
On 01/13/2015 07:35 AM, H.J. Lu wrote:
> Can I apply it to GCC trunk?
Please.
r~
Hi all,
This is a backport patch for
https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=213864
arm-none-eabi regression test has been done, no new issues.
Okay for branch 4.8?
gcc/ChangeLog
Fix PR target/61413
Backport from mainline.
2014-08-12 Ramana Radhakrishnan
PR target/61413
On 13/01/15 15:53, Renlin Li wrote:
> Hi all,
>
> This is a backport patch for
> https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=213864
>
> arm-none-eabi regression test has been done, no new issues.
> Okay for branch 4.8?
>
> gcc/ChangeLog
> Fix PR target/61413
> Backport from mainline.
Hi all,
This patch update CLZ_DEFINED_VALUE_AT_ZERO and
CTZ_DEFINED_VALUE_AT_ZERO to make them return 2 in
arm back-end.
Here are the explanations from GCC documentation:
CLZ_DEFINED_VALUE_AT_ZERO (mode, value)
CTZ_DEFINED_VALUE_AT_ZERO (mode, value)
A C expression that indicates whether the
On 13/01/15 15:58, Renlin Li wrote:
> Hi all,
>
> This patch update CLZ_DEFINED_VALUE_AT_ZERO and
> CTZ_DEFINED_VALUE_AT_ZERO to make them return 2 in
> arm back-end.
>
> Here are the explanations from GCC documentation:
>
> CLZ_DEFINED_VALUE_AT_ZERO (mode, value)
> CTZ_DEFINED_VALUE_AT_ZERO (m
On Mon, Jan 12, 2015 at 02:29:53PM -0700, Jeff Law wrote:
> On 01/12/15 12:59, Jakub Jelinek wrote:
> >Hi!
> >
> >As mentioned in the PR, giving up for all vector mode extensions
> >is unnecessary, but unlike scalar integer extensions, where the low part
> >of the extended value is the original val
Hi!
My PR60663 fix unfortunately stopped CSE of all inline-asms, even when
they e.g. only have the clobbers added by default.
This patch attempts to restore the old behavior, with the exceptions:
1) as always, asm volatile is not CSEd
2) inline-asm with multiple outputs are not CSEd
3) on request
On Mon, Jan 12, 2015 at 09:55:15PM +0100, Jakub Jelinek wrote:
> > specific changes from there.
>
> Yes, I'll try to cherry-pick those tomorrow.
>
> > I am especially interested in fixing these two issues, but there may be
> > other important improvements too:
> >
> >
> > https://gcc.gnu.org/b
> Hello.
>
> Following patch adds support for target and optimization nodes comparison,
> which is
> based on Honza's newly added infrastructure.
>
> Apart from that, there's a small hunk that corrects formatting and removes
> unnecessary
> call to a comparison function.
>
> Hope it can be app
Hi!
With VALUE attr, the PARM_DECLs hold the values and thus are (usually) not
read-only, therefore telling the middle-end they are read-only leads to
invalid IL.
Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for
trunk?
2015-01-13 Jakub Jelinek
PR fortran/64
We ICE on this testcase, because the usage of #pragma GCC ivdep
pulls in the ANNOTATE internal functions which don't have underlying
fndecls, hence we segv on a NULL_TREE. This patch makes get_attrs_for
be prepared for such a scenario. The callers of get_attrs_for already
check for NULL_TREE. I
Jakub Jelinek wrote:
> With VALUE attr, the PARM_DECLs hold the values and thus are (usually) not
> read-only, therefore telling the middle-end they are read-only leads to
> invalid IL.
>
> Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for
> trunk?
OK. Thanks for the pat
On 13 January 2015 at 16:06, Prathamesh Kulkarni
wrote:
> On 13 January 2015 at 15:34, Richard Biener wrote:
>> On Sun, 11 Jan 2015, Prathamesh Kulkarni wrote:
>>
>>> Hi,
>>> This is a revamped expr.h flattening flattening patch rebased on
>>> tree.h and tree-core.h flattening patch (r219402).
>>
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