Hi,
I am implementing a gcc backend for a target architecture which
contains assembly isntructions writing two result registers.
I have a difficulty implementing builtins for such instructions efficiently.
For example, the "super-load" instruction has a formsuper_ld32 rA
-> rX, rY.
This op
Hi, Paolo and Ian,
Thanks a lot for your suggestions. I have tried the one suggested by Paolo
It has improved my code considerably, disposing of load and stores.
However, the code produced is still not as efficient as I would like it to be
For the following function
int bar()
{
int r1, r2;
lo
Hi Paolo, thanks for the tip.
I tried it and things look different now, but I still didn't achieve
the desired efficiency. Now after subreg lowering the code looks like:
(insn 6 29 7 (parallel [
(set (subreg:SI (reg/v:DI 133 [ tmp ]) 0)
(unspec:SI [ (reg/f:SI 135)] 120
Hi, Paolo,
Your suggestion was right !
I have made an additional define_insn with two SImode destination
registers and now the lower_subreg pass is able to substitute
the subregs, and re-recognize the obtained instruction.
One small modification to your proposal is that
I create the original
