> -Original Message-
> From: Eric Botcazou [mailto:ebotca...@adacore.com]
> Sent: 27 November 2013 18:27
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: reg_nonzero_bits_for_combine misunderstood
>
> > But the problem is that if the mode of the register is larger than the mode
> >
> Right, didn't notice nonzero_sign_valid below. I think restricting mode ==
> last_set_mode is too restrictive.
>
> nonzero_bits is still valid if the new mode has less precision than the old
> mode.
Sure, but I'm not suggesting to restrict anything, quite the contrary:
{
unsigned HOS
> -Original Message-
> From: Eric Botcazou [mailto:ebotca...@adacore.com]
> Sent: 28 November 2013 11:27
> To: Paulo Matos
> Cc: gcc@gcc.gnu.org
> Subject: Re: reg_nonzero_bits_for_combine misunderstood
>
> > Right, didn't notice nonzero_sign_valid below. I think restricting mode ==
> > la
Hi,
This is a proposal to update x86-64 PLT for MPX.We don't
need to change GCC nor glibc to support it. The binutils change
is implemented on hjl/mpx/pltext8 branch. GDB works except
there are no synthetic symbols for the .plt section. Prelink change
is very small.
Any comments?
Thanks.
(Add gcc@gcc.gnu.org which is more relevant.)
After some investigation, I can answer my own question now.
On 11/11/13 16:39, Yufeng Zhang wrote:
Hi,
I'm trying to understand the following code-gen difference in the
following code:
#ifdef BEFORE
typedef int arr_2[4][5];
#else
typedef int arr_2
Snapshot gcc-4.8-20131128 is now available on
ftp://gcc.gnu.org/pub/gcc/snapshots/4.8-20131128/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 4.8 SVN branch
with the following options: svn://gcc.gnu.org/svn/gcc/branches
