[clang] [llvm] [NVPTX] Add intrinsics for redux.sync f32 instructions (PR #126664)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/126664 >From 88e076bb9af3b1bc63d76feef1ba842d88fbd95f Mon Sep 17 00:00:00 2001 From: Srinivasa Ravi Date: Mon, 10 Feb 2025 14:13:42 +0530 Subject: [PATCH] [NVPTX] Add intrinsics for redux.sync f32 instructions Adds

[clang] [llvm] [NVPTX] Add intrinsics for redux.sync f32 instructions (PR #126664)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/126664 >From 062a48e73ea1434f3c00ab3c0e717db66aa0f15e Mon Sep 17 00:00:00 2001 From: Srinivasa Ravi Date: Mon, 10 Feb 2025 14:13:42 +0530 Subject: [PATCH] [NVPTX] Add intrinsics for redux.sync f32 instructions Adds

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

@@ -580,6 +580,15 @@ def __nvvm_f2bf16_rz : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX70>; def __nvvm_f2bf16_rz_relu : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX70>; def __nvvm_f2tf32_rna : NVPTXBuiltinSMAndPTX<"int32_t(float)", SM_80, PTX70>; +def __nvvm_f2tf32_

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

https://github.com/Wolfram70 edited https://github.com/llvm/llvm-project/pull/134345 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

@@ -703,6 +703,53 @@ let hasSideEffects = false in { defm CVT_to_tf32_rz_satf : CVT_TO_TF32<"rz.satfinite", [hasPTX<86>, hasSM<100>]>; defm CVT_to_tf32_rn_relu_satf : CVT_TO_TF32<"rn.relu.satfinite", [hasPTX<86>, hasSM<100>]>; defm CVT_to_tf32_rz_relu_satf : CVT_TO_TF

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

@@ -1021,6 +1036,174 @@ __device__ void nvvm_cvt_sm89() { __nvvm_e5m2x2_to_f16x2_rn(0x4c4c); // CHECK_PTX81_SM89: call <2 x half> @llvm.nvvm.e5m2x2.to.f16x2.rn.relu(i16 19532) __nvvm_e5m2x2_to_f16x2_rn_relu(0x4c4c); + + // CHECK_PTX81_SM89: call i32 @llvm.nvvm.f2tf32.rn

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

https://github.com/Wolfram70 edited https://github.com/llvm/llvm-project/pull/134345 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/134345 >From c5f843152d035f4671d132d3844ea1f18be703fe Mon Sep 17 00:00:00 2001 From: Srinivasa Ravi Date: Wed, 5 Mar 2025 12:35:39 +0530 Subject: [PATCH] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants Th

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

@@ -1548,6 +1548,45 @@ let TargetPrefix = "nvvm" in { Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoMem, IntrNoCallback]>; def int_nvvm_e5m2x2_to_f16x2_rn_relu : ClangBuiltin<"__nvvm_e5m2x2_to_f16x2_rn_relu">, Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoM

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

https://github.com/Wolfram70 edited https://github.com/llvm/llvm-project/pull/134345 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

@@ -1548,6 +1548,45 @@ let TargetPrefix = "nvvm" in { Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoMem, IntrNoCallback]>; def int_nvvm_e5m2x2_to_f16x2_rn_relu : ClangBuiltin<"__nvvm_e5m2x2_to_f16x2_rn_relu">, Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoM

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

@@ -1944,6 +1944,62 @@ def : Pat<(int_nvvm_e5m2x2_to_f16x2_rn Int16Regs:$a), def : Pat<(int_nvvm_e5m2x2_to_f16x2_rn_relu Int16Regs:$a), (CVT_f16x2_e5m2x2 $a, CvtRN_RELU)>; +def : Pat<(int_nvvm_ff_to_e2m3x2_rn f32:$a, f32:$b), + (CVT_e2m3x2_f32 $a, $b, CvtRN)

[clang] [llvm] [clang][NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

https://github.com/Wolfram70 edited https://github.com/llvm/llvm-project/pull/134345 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

Wolfram70 wrote: @Artem-B and @AlexMaclean , could you please take another look to see if this change is good to go? https://github.com/llvm/llvm-project/pull/134345 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bi

[clang] [llvm] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants (PR #134345)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/134345 >From fdaf84496ae8f6b5213be8d568010b7f3c1d1aee Mon Sep 17 00:00:00 2001 From: Srinivasa Ravi Date: Wed, 5 Mar 2025 12:35:39 +0530 Subject: [PATCH] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants Th

[clang] [llvm] [clang][NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

Wolfram70 wrote: Added `-disable-llvm-optzns` to the new RUN lines in `builtins-nvptx.c` since I think some tests are failing due to changes from #134416 https://github.com/llvm/llvm-project/pull/134345 ___ cfe-commits mailing list cfe-commits@lists.

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/134345 >From 93757e155b631f4287b96d0b2ad7091371faba83 Mon Sep 17 00:00:00 2001 From: Srinivasa Ravi Date: Wed, 5 Mar 2025 12:35:39 +0530 Subject: [PATCH] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants Th

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

@@ -703,6 +703,46 @@ let hasSideEffects = false in { defm CVT_to_tf32_rz_satf : CVT_TO_TF32<"rz.satfinite", [hasPTX<86>, hasSM<100>]>; defm CVT_to_tf32_rn_relu_satf : CVT_TO_TF32<"rn.relu.satfinite", [hasPTX<86>, hasSM<100>]>; defm CVT_to_tf32_rz_relu_satf : CVT_TO_TF

[clang] [llvm] [clang][NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/134345 >From 18c6641b676ac90bfe300df48d0b8719df1f1add Mon Sep 17 00:00:00 2001 From: Srinivasa Ravi Date: Wed, 5 Mar 2025 12:35:39 +0530 Subject: [PATCH] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants Th

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

@@ -703,6 +703,53 @@ let hasSideEffects = false in { defm CVT_to_tf32_rz_satf : CVT_TO_TF32<"rz.satfinite", [hasPTX<86>, hasSM<100>]>; defm CVT_to_tf32_rn_relu_satf : CVT_TO_TF32<"rn.relu.satfinite", [hasPTX<86>, hasSM<100>]>; defm CVT_to_tf32_rz_relu_satf : CVT_TO_TF

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

@@ -1548,6 +1548,45 @@ let TargetPrefix = "nvvm" in { Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoMem, IntrNoCallback]>; def int_nvvm_e5m2x2_to_f16x2_rn_relu : ClangBuiltin<"__nvvm_e5m2x2_to_f16x2_rn_relu">, Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoM

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/134345 >From 648bfd77d48c395ae81a1d28fa6d925e1e75c02a Mon Sep 17 00:00:00 2001 From: Srinivasa Ravi Date: Wed, 5 Mar 2025 12:35:39 +0530 Subject: [PATCH] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants Th

[clang] [llvm] [NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/134345 >From 1f59834f760c7880bd958f82853f253816b1e653 Mon Sep 17 00:00:00 2001 From: Srinivasa Ravi Date: Wed, 5 Mar 2025 12:35:39 +0530 Subject: [PATCH] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants Th

[clang] [llvm] [clang][NVPTX] Add builtins and intrinsics for conversions of new FP types (PR #134345)

@@ -703,6 +703,41 @@ let hasSideEffects = false in { defm CVT_to_tf32_rz_satf : CVT_TO_TF32<"rz.satfinite", [hasPTX<86>, hasSM<100>]>; defm CVT_to_tf32_rn_relu_satf : CVT_TO_TF32<"rn.relu.satfinite", [hasPTX<86>, hasSM<100>]>; defm CVT_to_tf32_rz_relu_satf : CVT_TO_TF

[clang] [llvm] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants (PR #134345)

https://github.com/Wolfram70 created https://github.com/llvm/llvm-project/pull/134345 This change adds NVVM intrinsics and clang builtins for the cvt instruction variants of types `.e2m3x2`, `.e3m2x2`, and `.ue8m0x2` introduced in PTX 8.6 for `sm_100a`, `sm_101a`, and `sm_120a`. Tests are add

[clang] [llvm] [NVPTX] Add intrinsics and clang builtins for conversions of f4x2 type (PR #139244)

https://github.com/Wolfram70 edited https://github.com/llvm/llvm-project/pull/139244 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add intrinsics and clang builtins for conversions of f4x2 type (PR #139244)

https://github.com/Wolfram70 created https://github.com/llvm/llvm-project/pull/139244 This change adds intrinsics and cllang builtiins for the cvt instruction variants of type (FP4) `.e2m1x2`. introduced in PTX 8.6 for `sm_100a`, `sm_101a`, and `sm_120a`. Tests are added in `NVPTX/convert-sm1

[clang] [llvm] [NVPTX] Add intrinsics and clang builtins for conversions of f4x2 type (PR #139244)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/139244 >From 0f236de49493d7fb7c1ebee69065b15c9bc07eca Mon Sep 17 00:00:00 2001 From: Srinivasa Ravi Date: Wed, 7 May 2025 14:41:48 +0530 Subject: [PATCH] [NVPTX] Add intrinsics and clang builtins for conversions of

[clang] [llvm] [NVPTX] Add intrinsics and clang builtins for conversions of f4x2 type (PR #139244)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/139244 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans

[clang] [llvm] [NVPTX] Add intrinsics and clang builtins for conversions of f4x2 type (PR #139244)

https://github.com/Wolfram70 closed https://github.com/llvm/llvm-project/pull/139244 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add intrinsics and clang builtins for conversions of f4x2 type (PR #139244)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/139244 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans

[clang] [llvm] [NVPTX] Add intrinsics and clang builtins for conversions of f4x2 type (PR #139244)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/139244 >From 63b1be08a72815c3fc195ac2356a29b61ab6d1c7 Mon Sep 17 00:00:00 2001 From: Srinivasa Ravi Date: Wed, 7 May 2025 14:41:48 +0530 Subject: [PATCH] [NVPTX] Add intrinsics and clang builtins for conversions of

[clang] [llvm] [NVPTX] Add intrinsics and clang builtins for conversions of f4x2 type (PR #139244)

https://github.com/Wolfram70 updated https://github.com/llvm/llvm-project/pull/139244 >From a9588758d03a80ce055725d7d7db0b0deb685f96 Mon Sep 17 00:00:00 2001 From: Srinivasa Ravi Date: Wed, 7 May 2025 14:41:48 +0530 Subject: [PATCH] [NVPTX] Add intrinsics and clang builtins for conversions of