[PATCH] D158626: [AArch64] Add missing vrnd intrinsics

2023-08-23 Thread Max Iyengar via Phabricator via cfe-commits
miyengar created this revision. miyengar added a reviewer: vhscampos. Herald added subscribers: hiraditya, kristof.beyls. Herald added a project: All. miyengar requested review of this revision. Herald added projects: clang, LLVM. Herald added subscribers: llvm-commits, cfe-commits. This patch add

[PATCH] D158626: [AArch64] Add missing vrnd intrinsics

2023-09-07 Thread Max Iyengar via Phabricator via cfe-commits
miyengar updated this revision to Diff 556170. miyengar added a comment. Moved pattern from `AArchInstrFormats.td` to `AArchInstrInfo.td` CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158626/new/ https://reviews.llvm.org/D158626 Files: clang/include/clang/Basic/arm_neon.td clang/li

[PATCH] D158626: [AArch64] Add missing vrnd intrinsics

2023-09-07 Thread Max Iyengar via Phabricator via cfe-commits
miyengar added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:6309 + + def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn))), + (!cast(NAME # Dr) FPR64:$Rn)>; dmgreen wrote: > miyengar wrote: > > dmgreen wrote: > > > I think the ins

[PATCH] D158626: [AArch64] Add missing vrnd intrinsics

2023-08-24 Thread Max Iyengar via Phabricator via cfe-commits
miyengar updated this revision to Diff 553104. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158626/new/ https://reviews.llvm.org/D158626 Files: clang/include/clang/Basic/arm_neon.td clang/lib/CodeGen/CGBuiltin.cpp clang/test/CodeGen/aarch64-v

[PATCH] D158626: [AArch64] Add missing vrnd intrinsics

2023-08-24 Thread Max Iyengar via Phabricator via cfe-commits
miyengar marked an inline comment as done. miyengar added a comment. Thank you for the feedback! I've added an amended patch using the pre-existing instruction. Also, I've tried to submit the patch with context this time. Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats

[PATCH] D158626: [AArch64] Add missing vrnd intrinsics

2023-09-05 Thread Max Iyengar via Phabricator via cfe-commits
miyengar updated this revision to Diff 555879. miyengar marked an inline comment as done. miyengar added a comment. Moved v1f64 -> Dr (Vector to Scalar) Pattern from `SIMDTwoVectorSD` to `FRIntNNTVector` CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158626/new/ https://reviews.llvm.org

[PATCH] D158626: [AArch64] Add missing vrnd intrinsics

2023-09-05 Thread Max Iyengar via Phabricator via cfe-commits
miyengar added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:6309 + + def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn))), + (!cast(NAME # Dr) FPR64:$Rn)>; dmgreen wrote: > I think the instructions in this multiclass are the vect