Author: kito
Date: Thu Aug 23 20:05:08 2018
New Revision: 340595
URL: http://llvm.org/viewvc/llvm-project?rev=340595&view=rev
Log:
[RISCV] RISC-V using -fuse-init-array by default
Reviewers: asb, apazos, mgrang
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D50043
Modified:
Author: kito
Date: Tue Sep 17 01:09:56 2019
New Revision: 372078
URL: http://llvm.org/viewvc/llvm-project?rev=372078&view=rev
Log:
[RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly
RISC-V LLVM was only implement small/medlow code model, so it defined
__riscv_cmodel_medlow d
Author: kito
Date: Tue Sep 17 01:19:17 2019
New Revision: 372080
URL: http://llvm.org/viewvc/llvm-project?rev=372080&view=rev
Log:
[RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow
RISC-V GCC use -mcmodel=medany and -mcmodel=medlow, but LLVM use
-mcmodel=small and -mcmodel=medium.
@@ -106,6 +106,8 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zdinx", RISCVExtensionVersion{1, 0}},
+{"zexperimental", RISCVExtensionVersion{1, 0}},
+
kito-cheng wrote:
I guess we don't really need this dummy extension in RISC
https://github.com/kito-cheng approved this pull request.
Checked with `Generic_GCC::GCCInstallationDetector::init` to make sure clang
will use that to search gcc toolchain, so LGTM.
https://github.com/llvm/llvm-project/pull/71803
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@@ -7,534 +7,2189 @@
#include
-// CHECK-RV64-LABEL: define dso_local
@test_vundefined_f16mf4
-// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-LABEL: define dso_local
@test_vundefined_f16mf4(
+// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry
@@ -1,4 +1,4 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 3
kito-cheng wrote:
Does this cause those cha
https://github.com/kito-cheng approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/70354
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kito-cheng wrote:
short version: GCC isn't change.
long version: GCC's configure script isn't change, it's configure script in
riscv-gnu-toolchain
But I don't have strong opinion on this change since I believe user should
explicitly specify that, otherwise it's really to screw up to select mu
@@ -693,6 +693,13 @@ def HasStdExtZimop :
Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
+def FeatureStdExtZcmop : SubtargetFeature<"experi
kito-cheng wrote:
I would suggest set it as 0.1 rather than 1.0, and I gonna to ask Ved to add
version info as well...
https://github.com/llvm/llvm-project/pull/76893
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kito-cheng wrote:
And forgot to say: thanks for raise this issue! I didn't aware b extension is
back again until this PR created.
https://github.com/llvm/llvm-project/pull/76893
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kito-cheng wrote:
Issue created at riscv-b: https://github.com/riscv/riscv-b/issues/3
https://github.com/llvm/llvm-project/pull/76893
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kito-cheng wrote:
Hmmm, RISC-V ISA is growth after
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257 again, I
mean...we have zfinx and zdinx, which is also valid combination with
rv32e/rv64e, so we may need to revise ilp32e ABI again on the psABI side, but
my intention is not to b
kito-cheng wrote:
@wangpc-pp did you have interested on helping psABI side? it would be great if
you can help since I suspect I don't have enough bandwidth to deal with that
soon.
https://github.com/llvm/llvm-project/pull/76777
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@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR,
IdentifierInfo *II,
Author: Kito Cheng
Date: 2022-06-30T10:30:01+08:00
New Revision: 1b8cde9b633841c7199b345132423dd3d6bdf3e7
URL:
https://github.com/llvm/llvm-project/commit/1b8cde9b633841c7199b345132423dd3d6bdf3e7
DIFF:
https://github.com/llvm/llvm-project/commit/1b8cde9b633841c7199b345132423dd3d6bdf3e7.diff
LO
Author: Kito Cheng
Date: 2022-03-28T14:35:28+08:00
New Revision: ad57e10dbca2fdeff1448afc0aa1cf23d6df8736
URL:
https://github.com/llvm/llvm-project/commit/ad57e10dbca2fdeff1448afc0aa1cf23d6df8736
DIFF:
https://github.com/llvm/llvm-project/commit/ad57e10dbca2fdeff1448afc0aa1cf23d6df8736.diff
LO
Author: Kito Cheng
Date: 2022-07-26T15:47:47+08:00
New Revision: 7a5cb15ea6facd82756adafae76d60f36a0b60fd
URL:
https://github.com/llvm/llvm-project/commit/7a5cb15ea6facd82756adafae76d60f36a0b60fd
DIFF:
https://github.com/llvm/llvm-project/commit/7a5cb15ea6facd82756adafae76d60f36a0b60fd.diff
LO
Author: Kito Cheng
Date: 2022-04-08T15:09:03+08:00
New Revision: fc2d8326ae4d6e05c1aa2db7e7dbd8e759bf4d51
URL:
https://github.com/llvm/llvm-project/commit/fc2d8326ae4d6e05c1aa2db7e7dbd8e759bf4d51
DIFF:
https://github.com/llvm/llvm-project/commit/fc2d8326ae4d6e05c1aa2db7e7dbd8e759bf4d51.diff
LO
Author: Kito Cheng
Date: 2022-04-08T16:20:19+08:00
New Revision: f922dbb7923f73bab058d09346a2ec0b40ae3cb2
URL:
https://github.com/llvm/llvm-project/commit/f922dbb7923f73bab058d09346a2ec0b40ae3cb2
DIFF:
https://github.com/llvm/llvm-project/commit/f922dbb7923f73bab058d09346a2ec0b40ae3cb2.diff
LO
Author: Kito Cheng
Date: 2022-04-20T21:13:13+08:00
New Revision: f26c41e8dd28d86030cd0f5a6e9c11036acea5d2
URL:
https://github.com/llvm/llvm-project/commit/f26c41e8dd28d86030cd0f5a6e9c11036acea5d2
DIFF:
https://github.com/llvm/llvm-project/commit/f26c41e8dd28d86030cd0f5a6e9c11036acea5d2.diff
LO
Author: Kito Cheng
Date: 2022-04-30T11:09:12+08:00
New Revision: 02c7de3a4c32f2456df09df07e473bb95c85529c
URL:
https://github.com/llvm/llvm-project/commit/02c7de3a4c32f2456df09df07e473bb95c85529c
DIFF:
https://github.com/llvm/llvm-project/commit/02c7de3a4c32f2456df09df07e473bb95c85529c.diff
LO
Author: Kito Cheng
Date: 2022-04-30T11:10:44+08:00
New Revision: 41b951c92931b65c25485b224901d8cb00163b8e
URL:
https://github.com/llvm/llvm-project/commit/41b951c92931b65c25485b224901d8cb00163b8e
DIFF:
https://github.com/llvm/llvm-project/commit/41b951c92931b65c25485b224901d8cb00163b8e.diff
LO
Author: Kito Cheng
Date: 2022-05-16T15:13:05+08:00
New Revision: 7ff0bf576b841d5418c0fb1c4b94f16c6205e7d9
URL:
https://github.com/llvm/llvm-project/commit/7ff0bf576b841d5418c0fb1c4b94f16c6205e7d9
DIFF:
https://github.com/llvm/llvm-project/commit/7ff0bf576b841d5418c0fb1c4b94f16c6205e7d9.diff
LO
Author: Kito Cheng
Date: 2022-05-16T16:00:23+08:00
New Revision: 5bc469fd96192039bafe4bb9f74c85b37f63212e
URL:
https://github.com/llvm/llvm-project/commit/5bc469fd96192039bafe4bb9f74c85b37f63212e
DIFF:
https://github.com/llvm/llvm-project/commit/5bc469fd96192039bafe4bb9f74c85b37f63212e.diff
LO
Author: Kito Cheng
Date: 2022-05-18T23:14:29+08:00
New Revision: 1467e01f8f699fa2a69937dd07e51325ba71a93b
URL:
https://github.com/llvm/llvm-project/commit/1467e01f8f699fa2a69937dd07e51325ba71a93b
DIFF:
https://github.com/llvm/llvm-project/commit/1467e01f8f699fa2a69937dd07e51325ba71a93b.diff
LO
Author: Kito Cheng
Date: 2022-05-24T17:24:32+08:00
New Revision: b166aa833e44a5af6d6f39c34b79fe21b443e424
URL:
https://github.com/llvm/llvm-project/commit/b166aa833e44a5af6d6f39c34b79fe21b443e424
DIFF:
https://github.com/llvm/llvm-project/commit/b166aa833e44a5af6d6f39c34b79fe21b443e424.diff
LO
https://github.com/kito-cheng approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/84119
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kito-cheng wrote:
Add a testcase like AArch64 https://reviews.llvm.org/D150867 ?
https://github.com/llvm/llvm-project/pull/85899
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kito-cheng wrote:
There is some discussion in last (2024/2/29) LLVM sync up meeting: We all agree
that might not useful in linux target and those platforms disable GP
relaxation, like Android and fuchsia; However it's still useful for embedded
toolchain, so this change may surprise those embed
https://github.com/kito-cheng closed
https://github.com/llvm/llvm-project/pull/81727
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https://github.com/kito-cheng commented:
Could you add a testcase?
https://github.com/llvm/llvm-project/pull/83553
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https://github.com/kito-cheng edited
https://github.com/llvm/llvm-project/pull/77414
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kito-cheng wrote:
Does it possible to add testcases to demonstrate that can improve optimization?
https://github.com/llvm/llvm-project/pull/79975
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https://github.com/kito-cheng edited
https://github.com/llvm/llvm-project/pull/80201
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@@ -0,0 +1,76 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -relocation-model=static < %s | FileCheck %s
--check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -relocation-model=pic < %s | FileCheck %s
--check-prefix=RV6
https://github.com/kito-cheng approved this pull request.
Just one minor comment, otherwise LGTM :)
https://github.com/llvm/llvm-project/pull/80201
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kito-cheng wrote:
I guess we need add that at RVVEmitter::createbuilt...@riscvvemitter.cpp?
[1]
https://github.com/llvm/llvm-project/blob/main/clang/utils/TableGen/RISCVVEmitter.cpp#L418
[2]
https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/Builtins.h#L122-L124
[3]
http
kito-cheng wrote:
Also I guess most of RVV intrinsic could add `const` too, that could help some
generic optimization work better like CSE.
https://github.com/llvm/llvm-project/pull/79975
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https:/
kito-cheng wrote:
I am working on GCC part[1], and it's still under review, also @bemg is working
very closely with me :)
[1] https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642151.html
https://github.com/llvm/llvm-project/pull/78120
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kito-cheng wrote:
It tagged with 0.1 now :)
https://github.com/riscv/riscv-b/releases/tag/v0.1
https://github.com/llvm/llvm-project/pull/76893
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https://github.com/kito-cheng edited
https://github.com/llvm/llvm-project/pull/77560
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kito-cheng wrote:
LGTM for the RISC-V bits, thanks :)
https://github.com/llvm/llvm-project/pull/70262
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Author: Kito Cheng
Date: 2020-10-16T13:55:08+08:00
New Revision: cfa7094e49cfb7e37a84c0aa57c85c64c0581d17
URL:
https://github.com/llvm/llvm-project/commit/cfa7094e49cfb7e37a84c0aa57c85c64c0581d17
DIFF:
https://github.com/llvm/llvm-project/commit/cfa7094e49cfb7e37a84c0aa57c85c64c0581d17.diff
LO
Author: Kito Cheng
Date: 2021-07-14T14:25:02+08:00
New Revision: 5635d2a56dab6dc64d3a3f185d68f676b81dc736
URL:
https://github.com/llvm/llvm-project/commit/5635d2a56dab6dc64d3a3f185d68f676b81dc736
DIFF:
https://github.com/llvm/llvm-project/commit/5635d2a56dab6dc64d3a3f185d68f676b81dc736.diff
LO
Author: Kito Cheng
Date: 2021-03-04T14:17:54+08:00
New Revision: b46a1b129f684a230dd680341d198d8b11731812
URL:
https://github.com/llvm/llvm-project/commit/b46a1b129f684a230dd680341d198d8b11731812
DIFF:
https://github.com/llvm/llvm-project/commit/b46a1b129f684a230dd680341d198d8b11731812.diff
LO
Author: Kito Cheng
Date: 2022-10-27T23:53:32+08:00
New Revision: ae116f43ff140edfae166370ab6bc9ae3f556710
URL:
https://github.com/llvm/llvm-project/commit/ae116f43ff140edfae166370ab6bc9ae3f556710
DIFF:
https://github.com/llvm/llvm-project/commit/ae116f43ff140edfae166370ab6bc9ae3f556710.diff
LO
Author: Kito Cheng
Date: 2023-01-10T09:52:03+08:00
New Revision: f4c887c3a8406d85f4f942c8350f10026994f4d8
URL:
https://github.com/llvm/llvm-project/commit/f4c887c3a8406d85f4f942c8350f10026994f4d8
DIFF:
https://github.com/llvm/llvm-project/commit/f4c887c3a8406d85f4f942c8350f10026994f4d8.diff
LO
Author: Kito Cheng
Date: 2023-01-13T23:58:31+08:00
New Revision: f601039e8165cb2a49c783ccf4aafd1f7b326a63
URL:
https://github.com/llvm/llvm-project/commit/f601039e8165cb2a49c783ccf4aafd1f7b326a63
DIFF:
https://github.com/llvm/llvm-project/commit/f601039e8165cb2a49c783ccf4aafd1f7b326a63.diff
LO
@@ -2441,11 +2441,11 @@ define void @test_sf_vc_fvv_se_e16mf4( %vd,
; CHECK-NEXT:sf.vc.fvv 1, v8, v9, fa0
; CHECK-NEXT:ret
entry:
- tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1i16.f16.iXLen(iXLen 1,
%vd, %vs2, half %fs1, iXLen %vl)
+ tail call void @llvm.ris
https://github.com/kito-cheng commented:
The target is support LLVM IR part only, we would like to prevent expose that
on the C intrinsic level if possible, because that's intentionally to expose
vector with unsigned integer only.
https://github.com/llvm/llvm-project/pull/67094
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@@ -2524,11 +2551,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultRegIsFlagReg.push_back(IsFlagReg);
llvm::Type *Ty = ConvertTypeForMem(QTy);
+ ResultTruncRegTypes.push_back(Ty);
+
+ // Expressing the type as a structure in inline asm ca
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExt
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExt
https://github.com/kito-cheng approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/65762
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Author: Kito Cheng
Date: 2022-11-23T16:59:19+08:00
New Revision: 3fe89be8015955f2e8403f8b7d7580db13cedb2c
URL:
https://github.com/llvm/llvm-project/commit/3fe89be8015955f2e8403f8b7d7580db13cedb2c
DIFF:
https://github.com/llvm/llvm-project/commit/3fe89be8015955f2e8403f8b7d7580db13cedb2c.diff
LO
Author: Kito Cheng
Date: 2023-03-15T17:30:16+08:00
New Revision: 9b488ace17e6be64e61bf20f8ddc3eb563848bde
URL:
https://github.com/llvm/llvm-project/commit/9b488ace17e6be64e61bf20f8ddc3eb563848bde
DIFF:
https://github.com/llvm/llvm-project/commit/9b488ace17e6be64e61bf20f8ddc3eb563848bde.diff
LO
Author: Kito Cheng
Date: 2023-03-03T16:13:53+08:00
New Revision: be437f3bb8b657f4d2de4603734f24daa624d204
URL:
https://github.com/llvm/llvm-project/commit/be437f3bb8b657f4d2de4603734f24daa624d204
DIFF:
https://github.com/llvm/llvm-project/commit/be437f3bb8b657f4d2de4603734f24daa624d204.diff
LO
Author: Kito Cheng
Date: 2023-04-27T14:46:01+08:00
New Revision: da4fcb0c0b281746067f92d8804c18dbce4269bd
URL:
https://github.com/llvm/llvm-project/commit/da4fcb0c0b281746067f92d8804c18dbce4269bd
DIFF:
https://github.com/llvm/llvm-project/commit/da4fcb0c0b281746067f92d8804c18dbce4269bd.diff
LO
kito-cheng wrote:
RISC-V GCC has enabled `-fasynchronous-unwind-tables` and `-funwind-tables` by
default for Linux target, and disabled by default for baremetal, so generally
LGTM since it align the behavior with GCC, but I would like to wait @asb's
response.
NOTE: The patch[1] is come from
@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames()
const {
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// CSRs
- "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+ "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"
https://github.com/kito-cheng approved this pull request.
LGTM, and I would prefer wait one more LGTM from Craig or Philip *OR* wait one
more week to make sure no further comment :)
https://github.com/llvm/llvm-project/pull/85786
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https://github.com/kito-cheng approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/101472
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@@ -5554,6 +5554,17 @@ them if they use them.
}];
}
+def RISCVVLSCCDocs : Documentation {
+ let Category = DocCatCallingConvs;
+ let Heading = "riscv::vls_cc, riscv_vls_cc, clang::riscv_vls_cc";
+ let Content = [{
+The ``riscv_vls_cc`` attribute can be applied to a function.
@@ -317,38 +323,45 @@ ABIArgInfo
RISCVABIInfo::coerceAndExpandFPCCEligibleStruct(
// Fixed-length RVV vectors are represented as scalable vectors in function
// args/return and must be coerced from fixed vectors.
-ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const {
https://github.com/kito-cheng approved this pull request.
LGTM :)
https://github.com/llvm/llvm-project/pull/85899
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https://github.com/kito-cheng approved this pull request.
LGTM :)
https://github.com/llvm/llvm-project/pull/87966
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kito-cheng wrote:
It passed public review[1] and merged into riscv-isa-manual[2], so I think it's
time to mark it as 1.0 and moving forward :)
[1]
https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/KetVUCQkfK4/m/Y3Dbd2pvAAAJ?utm_medium=email&utm_source=footer
[2]
https://github.com/ris
kito-cheng wrote:
Could you add `B` into CombinedExtsEntry and added a test for that?
https://github.com/llvm/llvm-project/pull/76893
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kito-cheng wrote:
Jeff told me it's still need wait TSC vote for the ratification, anyway it will
ratify this month.
https://github.com/llvm/llvm-project/pull/76893
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kito-cheng wrote:
Could you give few more word on the description to mention we missed that in
the vector crpyto intrinsic proposal, and it's fixing but rather than
incompatible/breaking change for the intrinsic API?
https://github.com/llvm/llvm-project/pull/94318
_
https://github.com/kito-cheng approved this pull request.
https://github.com/llvm/llvm-project/pull/94318
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@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
}
static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"}, {"zks"}, {"zvkn"}, {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"}, {"zks"}, {"zvkn
kito-cheng wrote:
`llvm/docs/RISCVUsage.rst` need update
https://github.com/llvm/llvm-project/pull/88474
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@@ -119,6 +119,7 @@ on support follow.
``Za128rs`` Supported (`See note
<#riscv-profiles-extensions-note>`__)
``Za64rs``Supported (`See note
<#riscv-profiles-extensions-note>`__)
``Zacas`` Supported (`See note <#riscv-zacas-note>`__)
+
https://github.com/kito-cheng approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/88474
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kito-cheng wrote:
vfncvtbf16.c, vfwcvtbf16.c and vfwmaccbf16.c already in the LLVM repo, so I
think those files could removed from this PR?
https://github.com/llvm/llvm-project/pull/89354
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https:/
kito-cheng wrote:
> Oh, I forgot to remove them. Or do you think they should be moved to bfloat
> folder to make them consistent?
Remove files from this PR, that should be a separated NFC PR for moving those
files, but I am fine to keep those file in same place :)
https://github.com/llvm/llvm
https://github.com/kito-cheng approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/89354
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@@ -138,6 +155,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
+ RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
+
kito-cheng wr
kito-cheng wrote:
A test case will crash, missing `+` before `zbc`:
```
__attribute__((target_clones("default", "arch=+zbb,zbc;priority=-1",
"priority=-2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo1(void) { return
2; }
int bar() { return foo1(); }
```
```
$ clang -cc1 -triple riscv64-
@@ -391,7 +391,14 @@ void RISCVTargetInfo::fillValidTuneCPUList(
static void handleFullArchString(StringRef FullArchStr,
std::vector &Features) {
- Features.push_back("__RISCV_TargetAttrNeedOverride");
+
+ // Should be full arch string.
+ if
kito-cheng wrote:
I would suggest it should prefix with a vendor prefix, either `sf.vcix_state`
or `sifive.vcix_state`, also go `riscv-c-api-doc` or
`riscv-toolchain-conventions` :)
https://github.com/llvm/llvm-project/pull/106914
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kito-cheng wrote:
> Do you mean change the current vcix_state register to sf.vcix_state?
Yes, because it's SiFive specific register, other vendor may add other status
register like VCIX in future, so I would like to add prefix to make sure all
further similar stuff will follow same rule if pos
https://github.com/kito-cheng closed
https://github.com/llvm/llvm-project/pull/72463
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kito-cheng wrote:
Done by https://github.com/llvm/llvm-project/pull/71140
https://github.com/llvm/llvm-project/pull/72463
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https://github.com/kito-cheng approved this pull request.
LGTM :)
https://github.com/llvm/llvm-project/pull/95024
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kito-cheng wrote:
`llvm/docs/RISCVUsage.rst` and `llvm/docs/ReleaseNotes.rst` need update :)
https://github.com/llvm/llvm-project/pull/98891
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https://github.com/kito-cheng commented:
Don't forgot `llvm/docs/RISCVUsage.rst`, otherwise LGTM :P
https://github.com/llvm/llvm-project/pull/90818
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https://github.com/kito-cheng approved this pull request.
https://github.com/llvm/llvm-project/pull/92644
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https://github.com/kito-cheng approved this pull request.
LGTM as the original author of `SemaRISCVVectorLookup.cpp` :)
It's great to see we can put all RISC-V related stuff within same place rather
than many different files.
https://github.com/llvm/llvm-project/pull/92682
https://github.com/kito-cheng closed
https://github.com/llvm/llvm-project/pull/98855
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Author: Kito Cheng
Date: 2022-02-21T14:06:47+08:00
New Revision: 079d13668bf1b7f929f1897af90f64caae41c81d
URL:
https://github.com/llvm/llvm-project/commit/079d13668bf1b7f929f1897af90f64caae41c81d
DIFF:
https://github.com/llvm/llvm-project/commit/079d13668bf1b7f929f1897af90f64caae41c81d.diff
LO
Author: Kito Cheng
Date: 2022-02-21T14:25:49+08:00
New Revision: 0a17ee1ebe0c3384520ea14fdc1d33e38217341a
URL:
https://github.com/llvm/llvm-project/commit/0a17ee1ebe0c3384520ea14fdc1d33e38217341a
DIFF:
https://github.com/llvm/llvm-project/commit/0a17ee1ebe0c3384520ea14fdc1d33e38217341a.diff
LO
Author: Kito Cheng
Date: 2022-02-21T14:39:43+08:00
New Revision: 47b1fa5fc48821eefefd157ed4af2f2cf3bacef4
URL:
https://github.com/llvm/llvm-project/commit/47b1fa5fc48821eefefd157ed4af2f2cf3bacef4
DIFF:
https://github.com/llvm/llvm-project/commit/47b1fa5fc48821eefefd157ed4af2f2cf3bacef4.diff
LO
Author: Kito Cheng
Date: 2022-02-21T14:56:58+08:00
New Revision: cc279529e8317301492f9625b6acc9a0bf52db56
URL:
https://github.com/llvm/llvm-project/commit/cc279529e8317301492f9625b6acc9a0bf52db56
DIFF:
https://github.com/llvm/llvm-project/commit/cc279529e8317301492f9625b6acc9a0bf52db56.diff
LO
Author: Kito Cheng
Date: 2022-02-21T15:25:21+08:00
New Revision: c1f17b0a9ea0d467eaa9589cc28db2787efe3ebf
URL:
https://github.com/llvm/llvm-project/commit/c1f17b0a9ea0d467eaa9589cc28db2787efe3ebf
DIFF:
https://github.com/llvm/llvm-project/commit/c1f17b0a9ea0d467eaa9589cc28db2787efe3ebf.diff
LO
Author: Kito Cheng
Date: 2022-02-21T20:43:51+08:00
New Revision: 071a9b751a46205dc276069dfbc0d38582736990
URL:
https://github.com/llvm/llvm-project/commit/071a9b751a46205dc276069dfbc0d38582736990
DIFF:
https://github.com/llvm/llvm-project/commit/071a9b751a46205dc276069dfbc0d38582736990.diff
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