r339759 - Fix ASTMatchersTraversalTest testcase compile on older compilers

Author: dmgreen Date: Wed Aug 15 03:39:43 2018 New Revision: 339759 URL: http://llvm.org/viewvc/llvm-project?rev=339759&view=rev Log: Fix ASTMatchersTraversalTest testcase compile on older compilers Some versions of gcc, especially when invoked through ccache (-E), can have trouble with raw strin

r340398 - [AArch64] Add Tiny Code Model for AArch64

Author: dmgreen Date: Wed Aug 22 04:34:28 2018 New Revision: 340398 URL: http://llvm.org/viewvc/llvm-project?rev=340398&view=rev Log: [AArch64] Add Tiny Code Model for AArch64 Adds a tiny code model to Clang along side rL340397. Differential Revision: https://reviews.llvm.org/D49674 Modified:

r342053 - [CodeGen] Align rtti and vtable data

Author: dmgreen Date: Wed Sep 12 07:09:06 2018 New Revision: 342053 URL: http://llvm.org/viewvc/llvm-project?rev=342053&view=rev Log: [CodeGen] Align rtti and vtable data Previously the alignment on the newly created rtti/typeinfo data was largely not set, meaning that DataLayout::getPreferredAli

r338566 - [UnrollAndJam] Add unroll_and_jam pragma handling

Author: dmgreen Date: Wed Aug 1 07:36:12 2018 New Revision: 338566 URL: http://llvm.org/viewvc/llvm-project?rev=338566&view=rev Log: [UnrollAndJam] Add unroll_and_jam pragma handling This adds support for the unroll_and_jam pragma, to go with the recently added unroll and jam pass. The name of t

Re: r348020 - Reverting r347949-r347951 because they broke the test bots.

Hello! Did you intend to change the .gitignore here too? Cheers Dave From: cfe-commits on behalf of Aaron Ballman via cfe-commits Sent: 30 November 2018 18:52:51 To: cfe-commits@lists.llvm.org Subject: r348020 - Reverting r347949-r347951 because they broke

Re: r348020 - Reverting r347949-r347951 because they broke the test bots.

Thanks for the fix, And thanks for the work keeping the bots green! Dave From: Aaron Ballman Sent: 30 November 2018 19:35 To: David Green Cc: cfe-commits; nd Subject: Re: r348020 - Reverting r347949-r347951 because they broke the test bots.   On Fri, Nov 30, 2018 at 2:31 PM David Green w

r348582 - Add a AArch64 triple to tiny codemodel test.

Author: dmgreen Date: Fri Dec 7 03:16:03 2018 New Revision: 348582 URL: http://llvm.org/viewvc/llvm-project?rev=348582&view=rev Log: Add a AArch64 triple to tiny codemodel test. Most other targets do not support the tiny code model. Modified: cfe/trunk/test/CodeGen/codemodels.c Modified:

Re: r342053 - [CodeGen] Align rtti and vtable data

x27;m seeing test failures after this patch. I'm trying to get a test case reduced, but can we revert until we figure it out? Thanks! -eric On Wed, Sep 12, 2018 at 7:10 AM David Green via cfe-commits mailto:cfe-commits@lists.llvm.org>> wrote: Author: dmgreen Date: Wed Sep 12 0

Re: r342525 - [NFC] Fix uncompilable test cases of ExprMutationAnalyzer.

Thanks! That sorted us right out. Dave From: Shuai Wang Sent: 19 September 2018 21:32 To: David Green Cc: cfe-commits@lists.llvm.org Subject: Re: r342525 - [NFC] Fix uncompilable test cases of ExprMutationAnalyzer. On Wed, Sep 19, 2018 at 3:10 AM David Green mailto:david.gr...@arm.com>>

r343843 - [AArch64] Use filecheck captures for metadata node numbers in test. NFC

Author: dmgreen Date: Fri Oct 5 03:21:25 2018 New Revision: 343843 URL: http://llvm.org/viewvc/llvm-project?rev=343843&view=rev Log: [AArch64] Use filecheck captures for metadata node numbers in test. NFC Just a quick fix for cases where extra metadata members are present. Modified: cfe/tru

Re: r352055 - Fix failing buildbots

Hello Sorry for the late reply. I'm not sure this ifdef is quite correct. It will be testing the _host_ architecture, presuming the default target is the same. If they are different (for example if the default target is aarch64 on an x86 machine), the test will presumably still fail. I went lo

Re: r352055 - Fix failing buildbots

Hello I think, because this is a unit-test, the compile will happen for the host (x86_64 in this case). So the binary will still be x86_64. The compile that the test runs will pick up whatever the default target triple is (hexagon for the bot, aarch64 for us). I don't know a lot about these t

r352956 - [ASTImporter] Fix up test that only works on X86.

Author: dmgreen Date: Sat Feb 2 00:31:22 2019 New Revision: 352956 URL: http://llvm.org/viewvc/llvm-project?rev=352956&view=rev Log: [ASTImporter] Fix up test that only works on X86. The test will fail if the default target triple is not X86, even if the host platform is. So move the check into

Re: r352055 - Fix failing buildbots

Sounds good to me, easy enough for me to test here. And I'll count that as a review. I've given it a try in rC352956. We can see how that bot feels about it. Dave > Dave, > > The idea to check explicitly the triple inside the test function is quite > convincing. Will you try to fix it that w

r354201 - Move multiline raw string literal out of macro. NFC

Author: dmgreen Date: Sat Feb 16 03:19:04 2019 New Revision: 354201 URL: http://llvm.org/viewvc/llvm-project?rev=354201&view=rev Log: Move multiline raw string literal out of macro. NFC Certain combinations of gcc and ccache fail when the raw string literal is preprocessed. This just moves the st

r362814 - [ARM] Add ACLE feature macros for MVE.

Author: dmgreen Date: Fri Jun 7 10:28:12 2019 New Revision: 362814 URL: http://llvm.org/viewvc/llvm-project?rev=362814&view=rev Log: [ARM] Add ACLE feature macros for MVE. Fixup uninitialised variable. Modified: cfe/trunk/lib/Basic/Targets/ARM.cpp Modified: cfe/trunk/lib/Basic/Targets/ARM.

r367885 - [AST] Fix RecursiveASTVisitorTest multiline string literal. NFC

Author: dmgreen Date: Mon Aug 5 09:27:36 2019 New Revision: 367885 URL: http://llvm.org/viewvc/llvm-project?rev=367885&view=rev Log: [AST] Fix RecursiveASTVisitorTest multiline string literal. NFC Some compiler, notably older gccs (< 8) can have trouble with multiline raw string literals inside

r349059 - Fix CodeCompleteTest.cpp for older gcc plus ccache builds

Author: dmgreen Date: Thu Dec 13 09:20:06 2018 New Revision: 349059 URL: http://llvm.org/viewvc/llvm-project?rev=349059&view=rev Log: Fix CodeCompleteTest.cpp for older gcc plus ccache builds Some versions of gcc, especially when invoked through ccache (-E), can have trouble with raw string liter

Re: r349053 - [CodeComplete] Fill preferred type on binary expressions

Hello! Certain version of gcc (along with ccache iirc, where they use -E) don't like these raw strings literals inside macros. This happens: https://godbolt.org/g/fsXjB7 I've tried to fix it up in https://reviews.llvm.org/rL349059. My choice of variable nam

[clang] 7b3de1e - [ARM] Attempt to fixup MveEmitter warnings

Author: David Green Date: 2019-10-24T19:43:15+01:00 New Revision: 7b3de1e811972b874d91554642ccb2ef5b32eed6 URL: https://github.com/llvm/llvm-project/commit/7b3de1e811972b874d91554642ccb2ef5b32eed6 DIFF: https://github.com/llvm/llvm-project/commit/7b3de1e811972b874d91554642ccb2ef5b32eed6.diff L

[clang] 78700ef - [ARM] Fixup MVE intrinsic tests with no assert builds

Author: David Green Date: 2019-10-24T19:59:15+01:00 New Revision: 78700ef8866db7f5cea113fa81d810a28b5b7438 URL: https://github.com/llvm/llvm-project/commit/78700ef8866db7f5cea113fa81d810a28b5b7438 DIFF: https://github.com/llvm/llvm-project/commit/78700ef8866db7f5cea113fa81d810a28b5b7438.diff L

[clang] [AArch64] Add soft-float ABI (PR #74460)

@@ -534,7 +540,8 @@ Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr, QualType Ty, BaseTy = ArrTy->getElementType(); NumRegs = ArrTy->getNumElements(); } - bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy(); + bool IsFPR = Kind == AArch64ABIK

[libcxx] [clang] [flang] [compiler-rt] [llvm] [clang-tools-extra] [libcxxabi] [lldb] [mlir] [openmp] [MachineCopyPropagation] When the source of PreviousCopy is undef, we cannot replace sub register (

davemgreen wrote: Hello. I think that if you removed undef from the first instruction the result would still be incorrect. With: ``` $x8 = ORRXrs $xzr, $x0, 0, implicit $w0 $w8 = ORRWrs $wzr, $w0, 0, implicit-def $x8 ``` The second instruction will zero-extend the w0 register to x8. It would be

[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

@@ -899,6 +899,7 @@ Arm and AArch64 Support * Arm Cortex-A520 (cortex-a520). * Arm Cortex-A720 (cortex-a720). * Arm Cortex-X4 (cortex-x4). + * Arm Cortex-M52 (cortex-m52). davemgreen wrote: Is it worth splitting this list into one for -target=aarch64 an

[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

davemgreen wrote: CDE is enabled per decode block and probably doesn't make a lot of sense to enable universally. The cde options each pick between two features (CDE vs co-processor), and so isn't quite the same as on vs off. https://github.com/llvm/llvm-project/pull/74822

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

@@ -896,9 +896,13 @@ Arm and AArch64 Support Support has been added for the following processors (-mcpu identifiers in parenthesis): - * Arm Cortex-A520 (cortex-a520). - * Arm Cortex-A720 (cortex-a720). - * Arm Cortex-X4 (cortex-x4). + --target=arm + * Arm Cortex-M

[mlir] [lldb] [openmp] [llvm] [clang] [libcxxabi] [compiler-rt] [clang-tools-extra] [flang] [libcxx] [MachineCopyPropagation] When the source of PreviousCopy is undef, we cannot replace sub register (

davemgreen wrote: I don't believe the undef is the issue - I think the issue is that AArch64InstrInfo::isCopyInstrImpl is saying that a W-reg orr is a copy, even if it is really a zextend because the entire X output register is depended upon. Can you try and add something to isCopyInstImpl ins

[clang] [llvm] [llvm][ARM] Emit MVE .arch_extension after .fpu directive if it does not include MVE features (PR #71545)

https://github.com/davemgreen commented: Hi. From what I can tell the logic looks OK. We add the archextension in places we expect to now? It is generally considered best practice to not have clang test that run the entire pass pipeline. In this case it looks like it's trying to SLP vectorize

[llvm] [clang] [llvm][ARM] Emit MVE .arch_extension after .fpu directive if it does not include MVE features (PR #71545)

https://github.com/davemgreen edited https://github.com/llvm/llvm-project/pull/71545 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [llvm][ARM] Emit MVE .arch_extension after .fpu directive if it does not include MVE features (PR #71545)

@@ -0,0 +1,35 @@ +// RUN: %clang --target=arm-none-eabi -mcpu=cortex-m85 -mfloat-abi=hard -O2 -save-temps=obj -S -o - %s | FileCheck %s +// RUN: %clang --target=arm-none-eabi -mcpu=cortex-m55 -mfloat-abi=hard -O2 -save-temps=obj -S -o - %s | FileCheck %s + +// The below tests ar

[clang] [llvm] [llvm][ARM] Emit MVE .arch_extension after .fpu directive if it does not include MVE features (PR #71545)

https://github.com/davemgreen approved this pull request. Thanks. LGTM https://github.com/llvm/llvm-project/pull/71545 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [llvm] [clang] [MachineLICM][AArch64] Hoist COPY instructions with other uses in the loop (PR #71403)

@@ -1262,6 +1262,18 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI, return false; } + // If we have a COPY with other uses in the loop, hoist to allow the users to davemgreen wrote: Hello. From what I've seen in our benchmarks this has

[clang] [llvm] [clang-tools-extra] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,839 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [clang-tools-extra] [llvm] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,839 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang-tools-extra] [clang] [llvm] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,839 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [clang-tools-extra] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,839 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang-tools-extra] [clang] [llvm] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,839 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[llvm] [clang] [clang-tools-extra] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,839 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[openmp] [clang-tools-extra] [libcxx] [mlir] [clang] [compiler-rt] [lldb] [llvm] [libcxxabi] [flang] [MachineCopyPropagation] When the source of PreviousCopy is undef, we cannot replace sub register (

davemgreen wrote: Thanks. It sounds like there are not a lot of code changes, which is a good sign. I didn't expect the debug problems though. I'll try and take a look at the patch. Perhaps you are right that we need a new method for the debug info to use. https://github.com/llvm/llvm-project

[llvm] [clang-tools-extra] [LoopVectorize] Enable hoisting of runtime checks by default (PR #71538)

https://github.com/davemgreen approved this pull request. With that fixed, and from the perf Ive seen, this LGTM. Thanks https://github.com/llvm/llvm-project/pull/71538 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-

[clang] [llvm] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

@@ -81,6 +81,15 @@ static bool DecodeAArch64Features(const Driver &D, StringRef text, else return false; +// +jsconv and +complxnum implies +neon and +fp-armv8 davemgreen wrote: I believe this ideally would not be in the driver, as it does not

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

davemgreen wrote: It looks like there is a downstream implementation of this that was never upstreamed. Perhaps someone can fish it out for you to show how it looked? It might be using the wrong predefined macro, but does have some tests. https://github.com/llvm/llvm-project/pull/75440 ___

[clang] [llvm] [clang-tools-extra] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

https://github.com/davemgreen edited https://github.com/llvm/llvm-project/pull/72273 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [clang] [llvm] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[llvm] [clang-tools-extra] [clang] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [clang-tools-extra] [llvm] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

https://github.com/davemgreen commented: Thanks. I think it is worth trying to get this in. I already see it triggering in a number of places, it might be worth working on making it a little more generic in followup patches if we can, but there is already quite a bit going on. https://github.

[llvm] [clang-tools-extra] [clang] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [clang-tools-extra] [llvm] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang-tools-extra] [llvm] [clang] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [clang-tools-extra] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [clang-tools-extra] [llvm] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[llvm] [clang-tools-extra] [clang] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [clang-tools-extra] [llvm] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[llvm] [clang-tools-extra] [clang] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[llvm] [clang-tools-extra] [clang] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[compiler-rt] [clang] [libc] [llvm] [lldb] [clang-tools-extra] [flang] [mlir] [DAGCombiner] Combine frem into fdiv+ftrunc+fma (PR #67642)

davemgreen wrote: Do you have any analysis on the expected magnitude of the inaccuracy we might expect from performing the fdiv/trunc/fma vs the call to fmod? https://github.com/llvm/llvm-project/pull/67642 ___ cfe-commits mailing list cfe-commits@lis

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

davemgreen wrote: Let me try and get the downstream version, you might be able to pick up some things from it. A test at least should probably be present. https://github.com/llvm/llvm-project/pull/75440 ___ cfe-commits mailing list cfe-commits@lists.l

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

davemgreen wrote: This is the downstream code we have: https://gist.github.com/davemgreen/e7ade833274a60e975e67a66eda7cb44 Note that the __ARM_TARGET_COPROC_XYZ macros are probably wrong. They should be __ARM_FEATURE_COPROC bitfield macros according to the ACLE. Can you make use of some of tha

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

davemgreen wrote: Thanks for doing this. I think that __ARM_FEATURE_COPROC should be a bitfield, as defined in https://arm-software.github.io/acle/main/acle.html#coprocessor-intrinsics. That would remove the need for the other macros. https://github.com/llvm/llvm-project/pull/75440 ___

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

https://github.com/davemgreen commented: Thanks. This is looking good to me. I just have a few comments about different architecture revisions. https://github.com/llvm/llvm-project/pull/75440 ___ cfe-commits mailing list cfe-commits@lists.llvm.org htt

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

@@ -836,6 +837,70 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts, if (Opts.RWPI) Builder.defineMacro("__ARM_RWPI", "1"); + // Macros for enabling co-proc intrinsics + uint64_t FeatureCoprocBF = 0; + switch (ArchKind) { + default: +break; + case

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

@@ -836,6 +837,70 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts, if (Opts.RWPI) Builder.defineMacro("__ARM_RWPI", "1"); + // Macros for enabling co-proc intrinsics + uint64_t FeatureCoprocBF = 0; + switch (ArchKind) { + default: +break; + case

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

@@ -756,6 +756,58 @@ __arm_st64bv0(void *__addr, data512_t __value) { __builtin_arm_mops_memset_tag(__tagged_address, __value, __size) #endif +/* Coprocessor Intrinsics */ +#if defined(__ARM_FEATURE_COPROC) + +#if (__ARM_FEATURE_COPROC & 0x1) + +#if (__ARM_ARCH != 8) ---

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

https://github.com/davemgreen edited https://github.com/llvm/llvm-project/pull/75440 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

@@ -836,6 +837,70 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts, if (Opts.RWPI) Builder.defineMacro("__ARM_RWPI", "1"); + // Macros for enabling co-proc intrinsics + uint64_t FeatureCoprocBF = 0; + switch (ArchKind) { + default: +break; + case

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

davemgreen wrote: If you can make armv9-a work the same as armv8-a and add some tests for it then this LGTM https://github.com/llvm/llvm-project/pull/75440 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/

[clang-tools-extra] [clang] [llvm] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

https://github.com/davemgreen edited https://github.com/llvm/llvm-project/pull/72273 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [clang-tools-extra] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

@@ -0,0 +1,816 @@ +//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[llvm] [clang] [clang-tools-extra] [AArch64] Add an AArch64 pass for loop idiom transformations (PR #72273)

https://github.com/davemgreen approved this pull request. Thanks for the updates. From what I can tell this LGTM, but it will need a rebase. You might want to commit it with the option disabled, and then flip the switch in a followup to avoid the commit-revert cycles in case there are any issu

[clang] [ARM] arm_acle.h add Coprocessor Instrinsics (PR #75440)

https://github.com/davemgreen approved this pull request. Thanks. LGTM https://github.com/llvm/llvm-project/pull/75440 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] 3b09e53 - [ARM] Remove duplicate fp16 intrinsics

Author: David Green Date: 2022-07-28T14:26:17+01:00 New Revision: 3b09e532ee396bb07820ecadb29e1ed88f6e6c25 URL: https://github.com/llvm/llvm-project/commit/3b09e532ee396bb07820ecadb29e1ed88f6e6c25 DIFF: https://github.com/llvm/llvm-project/commit/3b09e532ee396bb07820ecadb29e1ed88f6e6c25.diff L

[clang] ef9df0d - [ARM] Simplify ArchGuard predicates in arm_neon.h.

Author: David Green Date: 2022-08-01T08:20:23+01:00 New Revision: ef9df0dc000c2c294398ab6fe13533d967dc29cd URL: https://github.com/llvm/llvm-project/commit/ef9df0dc000c2c294398ab6fe13533d967dc29cd DIFF: https://github.com/llvm/llvm-project/commit/ef9df0dc000c2c294398ab6fe13533d967dc29cd.diff L

[clang] 8c30f4a - [AArch64] Always allow the __bf16 type

Author: David Green Date: 2022-08-04T18:35:27+01:00 New Revision: 8c30f4a5ab3e8dc4a75669d497723f9a2d8d39c8 URL: https://github.com/llvm/llvm-project/commit/8c30f4a5ab3e8dc4a75669d497723f9a2d8d39c8 DIFF: https://github.com/llvm/llvm-project/commit/8c30f4a5ab3e8dc4a75669d497723f9a2d8d39c8.diff L

[clang] 9727c77 - [NFC] Rename Instrinsic to Intrinsic

Author: David Green Date: 2022-04-25T18:13:23+01:00 New Revision: 9727c77d58ac920a4158d08c15659470e52ddda4 URL: https://github.com/llvm/llvm-project/commit/9727c77d58ac920a4158d08c15659470e52ddda4 DIFF: https://github.com/llvm/llvm-project/commit/9727c77d58ac920a4158d08c15659470e52ddda4.diff L

[clang] 64816e6 - [AArch64] Support for Ampere1 core

Author: Philipp Tomsich Date: 2022-05-03T15:54:02+01:00 New Revision: 64816e68f4419a9e14c23be8aa96fa412bed7e12 URL: https://github.com/llvm/llvm-project/commit/64816e68f4419a9e14c23be8aa96fa412bed7e12 DIFF: https://github.com/llvm/llvm-project/commit/64816e68f4419a9e14c23be8aa96fa412bed7e12.dif

[clang] [clang][AArch64] Enable fp128 for aarch64 linux target (PR #85070)

https://github.com/davemgreen commented: Hi - I think this looks sensible, considering that long double == fp128. Should we be doing the same for other OS's in this file too? https://github.com/llvm/llvm-project/pull/85070 ___ cfe-commits mailing lis

[clang] [llvm] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (PR #85401)

@@ -67,6 +67,8 @@ Changes to Interprocedural Optimizations Changes to the AArch64 Backend -- +* Added support for Cortex-A520AE and Cortex-A720AE CPUs. davemgreen wrote: Could this have Cortex-A78AE too? https://github.com/llvm/ll

[clang] [llvm] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (PR #85401)

@@ -58,6 +58,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { CortexA55, CortexA510, CortexA520, +CortexA520AE, davemgreen wrote: These might not be worth adding, considering they should be the same as CortexA520, and coul

[clang] [llvm] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (PR #85401)

https://github.com/davemgreen approved this pull request. Thanks. LGTM https://github.com/llvm/llvm-project/pull/85401 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [ARM] __ARM_ARCH macro definition fix (PR #81493)

davemgreen wrote: I'm a little worried people might be relying on the existing behaviour, with both clang and GCC having this wrong for a while. If we are going to do it can you add a release note to clang explaining the new behaviour? https://github.com/llvm/llvm-project/pull/81493 __

[flang] [compiler-rt] [clang] [llvm] [mlir] [clang-tools-extra] [lldb] [libc] [libcxx] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)

davemgreen wrote: I see. The issue is that the opposite is often true as well - if we add a target specific intrinsic for this then, whilst we get a single instruction being emitted, we don't see all the other optimizations that the compiler can and should be performing. Things like constant

[clang] [clang-tools-extra] [compiler-rt] [llvm] [flang] [TTI]Fallback to SingleSrcPermute shuffle kind, if no direct estimation for (PR #79837)

davemgreen wrote: I think this is probably OK for Arm & AArch64. In the long run we should ideally be adding better extract subvector costs, but this patch moves the cost in that direction. https://github.com/llvm/llvm-project/pull/79837 ___ cfe-comm

[llvm] [clang-tools-extra] [clang] [AArch64] Implement -fno-plt for SelectionDAG/GlobalISel (PR #78890)

@@ -201,17 +201,27 @@ define dso_local void @rv_marker_3() personality ptr @__gxx_personality_v0 { ; GISEL-NEXT:bl _objc_object ; GISEL-NEXT: Ltmp1: ; GISEL-NEXT: ; %bb.1: ; %invoke.cont -; GISEL-NEXT:ldp x29, x30, [sp, #16] ; 16-byte Folded Reload +; GISEL-NEXT: Ll

[llvm] [clang] [AArch64][TargetParser] Add mcpu alias for Microsoft Azure Cobalt 100. (PR #79614)

davemgreen wrote: It looks like this needs to update testAArch64CPUArchList too. Otherwise it LGTM https://github.com/llvm/llvm-project/pull/79614 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/c

[libc] [clang-tools-extra] [lldb] [flang] [mlir] [llvm] [clang] [compiler-rt] [libcxx] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)

davemgreen wrote: Hello. Can you explain why this is needed, as opposed to using the equivalent shift/and/ors? https://github.com/llvm/llvm-project/pull/79672 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailm

[clang-tools-extra] [compiler-rt] [libc] [flang] [mlir] [libcxx] [lldb] [llvm] [clang] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)

davemgreen wrote: OK. We would not usually add intrinsics like this without a strong motivating case, that could not be optimized in some other way. It is better to use target independent options when available, and inline assembly is available as a fallback if it is really needed. But I would

[clang] [llvm] [AArch64][TargetParser] Add mcpu alias for Microsoft Azure Cobalt 100. (PR #79614)

https://github.com/davemgreen approved this pull request. Thanks. LGTM too. https://github.com/llvm/llvm-project/pull/79614 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [llvm] [clang] [AArch64][SVE2] Lower OR to SLI/SRI (PR #77555)

https://github.com/davemgreen approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77555 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

https://github.com/davemgreen approved this pull request. https://github.com/ARM-software/acle/pull/279 was committed recently, where I think this lines up with the final version of it. I think this LGTM in that case. https://github.com/llvm/llvm-project/pull/75516

[clang] 170de3d - [ParserTest] Move raw string literal out of macro

Author: David Green Date: 2020-01-05T11:24:04Z New Revision: 170de3de2eea8eb7f514dfa64d3f845ef10d8425 URL: https://github.com/llvm/llvm-project/commit/170de3de2eea8eb7f514dfa64d3f845ef10d8425 DIFF: https://github.com/llvm/llvm-project/commit/170de3de2eea8eb7f514dfa64d3f845ef10d8425.diff LOG: [

[clang] ab2ed8b - [SVE] Regenerate sve vector bits tests. NFC

Author: David Green Date: 2020-09-11T18:51:57+01:00 New Revision: ab2ed8bce9e924a2fc734ca4369419c18d124043 URL: https://github.com/llvm/llvm-project/commit/ab2ed8bce9e924a2fc734ca4369419c18d124043 DIFF: https://github.com/llvm/llvm-project/commit/ab2ed8bce9e924a2fc734ca4369419c18d124043.diff L

[clang] 667e800 - [ARM] Remove -O3 from mve intrinsic tests. NFC

Author: David Green Date: 2020-09-06T13:19:55+01:00 New Revision: 667e800bb3a8c1bdda0cabad7549c766b3424064 URL: https://github.com/llvm/llvm-project/commit/667e800bb3a8c1bdda0cabad7549c766b3424064 DIFF: https://github.com/llvm/llvm-project/commit/667e800bb3a8c1bdda0cabad7549c766b3424064.diff L

[clang] a15bd0b - [AIX] Add REQUIRES for powerpc test. NFC

Author: David Green Date: 2020-10-08T18:40:09+01:00 New Revision: a15bd0bfc20c2b2955c59450a67b6e8efe89c708 URL: https://github.com/llvm/llvm-project/commit/a15bd0bfc20c2b2955c59450a67b6e8efe89c708 DIFF: https://github.com/llvm/llvm-project/commit/a15bd0bfc20c2b2955c59450a67b6e8efe89c708.diff L

[clang] 40ce58d - Revert "[clang] Refactor AST printing tests to share more infrastructure"

Author: David Green Date: 2021-07-14T04:40:47+01:00 New Revision: 40ce58d0ca10a1195da82895749b67f30f000243 URL: https://github.com/llvm/llvm-project/commit/40ce58d0ca10a1195da82895749b67f30f000243 DIFF: https://github.com/llvm/llvm-project/commit/40ce58d0ca10a1195da82895749b67f30f000243.diff L

[clang] 0b83a18 - [AArch64] Enablement of Cortex-X2

Author: Mubashar Ahmad Date: 2021-11-01T11:55:24Z New Revision: 0b83a18a2b9db9c23082e8751c3a66ef37fc626f URL: https://github.com/llvm/llvm-project/commit/0b83a18a2b9db9c23082e8751c3a66ef37fc626f DIFF: https://github.com/llvm/llvm-project/commit/0b83a18a2b9db9c23082e8751c3a66ef37fc626f.diff LOG

[clang] 5ae949a - [Clang][ARM] Reenable arm_acle.c test.

Author: David Green Date: 2021-03-12T19:21:21Z New Revision: 5ae949a9276542b46f41374fbe7aee01e480d9d6 URL: https://github.com/llvm/llvm-project/commit/5ae949a9276542b46f41374fbe7aee01e480d9d6 DIFF: https://github.com/llvm/llvm-project/commit/5ae949a9276542b46f41374fbe7aee01e480d9d6.diff LOG: [

[clang] 2b3c813 - [Clang][ARM] Reenable arm_acle.c test.

Author: David Green Date: 2021-03-14T10:59:24Z New Revision: 2b3c8131434374caf3825c2bd4e012c85f8128de URL: https://github.com/llvm/llvm-project/commit/2b3c8131434374caf3825c2bd4e012c85f8128de DIFF: https://github.com/llvm/llvm-project/commit/2b3c8131434374caf3825c2bd4e012c85f8128de.diff LOG: [

[clang] 6f1e430 - [AArch64] Alter v8.5a FRINT neon intrinsics to be target-based, not preprocessor based

Author: David Green Date: 2022-10-24T11:22:06+01:00 New Revision: 6f1e430360591e22fb163ec77b78efd2de4c1d95 URL: https://github.com/llvm/llvm-project/commit/6f1e430360591e22fb163ec77b78efd2de4c1d95 DIFF: https://github.com/llvm/llvm-project/commit/6f1e430360591e22fb163ec77b78efd2de4c1d95.diff L

[clang] 9c48b7f - [AArch64][ARM] Alter v8.1a neon intrinsics to be target-based, not preprocessor based

Author: David Green Date: 2022-10-25T09:02:52+01:00 New Revision: 9c48b7f0e7a96e126a369d6036eff1bb259116c8 URL: https://github.com/llvm/llvm-project/commit/9c48b7f0e7a96e126a369d6036eff1bb259116c8 DIFF: https://github.com/llvm/llvm-project/commit/9c48b7f0e7a96e126a369d6036eff1bb259116c8.diff L

[clang] af1bb28 - [AArch64][ARM] Alter v8.3a complex neon intrinsics to be target-based, not preprocessor based

Author: David Green Date: 2022-10-25T14:35:11+01:00 New Revision: af1bb287b4de3c5a5d82679ceb001c7d70f09c82 URL: https://github.com/llvm/llvm-project/commit/af1bb287b4de3c5a5d82679ceb001c7d70f09c82 DIFF: https://github.com/llvm/llvm-project/commit/af1bb287b4de3c5a5d82679ceb001c7d70f09c82.diff L

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