https://git.reactos.org/?p=reactos.git;a=commitdiff;h=478348ead113ae5d5b5eaf579b540f65339bebbd
commit 478348ead113ae5d5b5eaf579b540f65339bebbd Author: Alex Ionescu <[email protected]> AuthorDate: Sun Jan 28 16:29:43 2018 +0100 Commit: Alex Ionescu <[email protected]> CommitDate: Sun Jan 28 16:29:43 2018 +0100 [ROSLOAD]: Fix NX enabling [ROSLOAD]: The IA32_MISC_ENABLE MSR bit actually _disables_ NX, so diabling the bit _enables_ NX. [ROSLOAD]: The MSR_XD_ENABLE_MASK is for the _high_ DWORD of the MSR (bit 34), not the low. [ROSLOAD]: Fix printf. [ENVIRON/ROSLOAD]: Switch to CPU_INFO structure instead of blindly using INT[4]. Revealed a bug in the PAE detection which was reading out of bounds. --- boot/environ/app/rosload/rosload.c | 39 ++++++++++++++++++++------------------ boot/environ/include/bl.h | 2 +- boot/environ/lib/misc/util.c | 30 ++++++++++++++--------------- boot/environ/lib/mm/i386/mmx86.c | 6 +++--- 4 files changed, 40 insertions(+), 37 deletions(-) diff --git a/boot/environ/app/rosload/rosload.c b/boot/environ/app/rosload/rosload.c index 9120631a1f..3c51963251 100644 --- a/boot/environ/app/rosload/rosload.c +++ b/boot/environ/app/rosload/rosload.c @@ -9783,24 +9783,26 @@ OslpMain ( _Out_ PULONG ReturnFlags ) { - INT CpuInfo[4]; - BOOLEAN NxDisabled; + CPU_INFO CpuInfo; + BOOLEAN NxEnabled; NTSTATUS Status; BOOLEAN ExecuteJump; + LARGE_INTEGER miscMsr; /* Check if the CPU supports NX */ - BlArchCpuId(0x80000001, 0, CpuInfo); - if (!(CpuInfo[3] & 0x10000)) + BlArchCpuId(0x80000001, 0, &CpuInfo); + if (!(CpuInfo.Edx & 0x10000)) { /* It doesn't, check if this is Intel */ - EfiPrintf(L"NX disabled: %d\r\n"); + EfiPrintf(L"NX disabled: %lx\r\n", CpuInfo.Edx); if (BlArchGetCpuVendor() == CPU_INTEL) { - /* Then turn off the MSR feature for it */ - EfiPrintf(L"NX being turned off\r\n"); - __writemsr(MSR_IA32_MISC_ENABLE, - __readmsr(MSR_IA32_MISC_ENABLE) & MSR_XD_ENABLE_MASK); - NxDisabled = TRUE; + /* Then turn off the MSR disable feature for it, enabling NX */ + EfiPrintf(L"NX being turned on\r\n"); + miscMsr.QuadPart = __readmsr(MSR_IA32_MISC_ENABLE); + miscMsr.HighPart &= MSR_XD_ENABLE_MASK; + __writemsr(MSR_IA32_MISC_ENABLE, miscMsr.QuadPart); + NxEnabled = TRUE; } } @@ -9818,12 +9820,13 @@ OslpMain ( /* Retore NX support */ __writemsr(MSR_EFER, __readmsr(MSR_EFER) ^ MSR_NXE); - /* Did we disable NX? */ - if (NxDisabled) + /* Did we manually enable NX? */ + if (NxEnabled) { - /* Turn it back on */ - __writemsr(MSR_IA32_MISC_ENABLE, - __readmsr(MSR_IA32_MISC_ENABLE) | ~MSR_XD_ENABLE_MASK); + /* Turn it back off */ + miscMsr.QuadPart = __readmsr(MSR_IA32_MISC_ENABLE); + miscMsr.HighPart |= ~MSR_XD_ENABLE_MASK; + __writemsr(MSR_IA32_MISC_ENABLE, miscMsr.QuadPart); } /* Go back */ @@ -9853,7 +9856,7 @@ OslMain ( NTSTATUS Status; PBL_RETURN_ARGUMENTS ReturnArguments; PBL_APPLICATION_ENTRY AppEntry; - INT CpuInfo[4]; + CPU_INFO CpuInfo; ULONG Flags; #ifdef DRAW_LOGO EFI_GRAPHICS_OUTPUT_BLT_PIXEL* gopBlt; @@ -9887,10 +9890,10 @@ OslMain ( if (BlArchIsCpuIdFunctionSupported(1)) { /* Query CPU features */ - BlArchCpuId(1, 0, CpuInfo); + BlArchCpuId(1, 0, &CpuInfo); /* Check if PAE is supported */ - if (CpuInfo[4] & 0x40) + if (CpuInfo.Edx & 0x40) { EfiPrintf(L"PAE Supported, but won't be used\r\n"); } diff --git a/boot/environ/include/bl.h b/boot/environ/include/bl.h index 7fa6c9667e..023e676d75 100644 --- a/boot/environ/include/bl.h +++ b/boot/environ/include/bl.h @@ -1666,7 +1666,7 @@ VOID BlArchCpuId ( _In_ ULONG Function, _In_ ULONG SubFunction, - _Out_ INT* Result + _Out_ PCPU_INFO Result ); CPU_VENDORS diff --git a/boot/environ/lib/misc/util.c b/boot/environ/lib/misc/util.c index d6e5459882..18f21cc2e9 100644 --- a/boot/environ/lib/misc/util.c +++ b/boot/environ/lib/misc/util.c @@ -904,12 +904,12 @@ BlArchGetPerformanceCounter ( ) { #if defined(_M_IX86) || defined(_M_X64) - INT CpuInfo[4]; + CPU_INFO CpuInfo; /* Serialize with CPUID, if it exists */ if (Archx86IsCpuidSupported()) { - BlArchCpuId(0, 0, CpuInfo); + BlArchCpuId(0, 0, &CpuInfo); } /* Read the TSC */ @@ -924,12 +924,12 @@ VOID BlArchCpuId ( _In_ ULONG Function, _In_ ULONG SubFunction, - _Out_ INT* Result + _Out_ PCPU_INFO Result ) { #if defined(_M_IX86) || defined(_M_X64) /* Use the intrinsic */ - __cpuidex(Result, Function, SubFunction); + __cpuidex((INT*)Result->AsUINT32, Function, SubFunction); #endif } @@ -938,37 +938,37 @@ BlArchGetCpuVendor ( VOID ) { - INT CpuInfo[4]; + CPU_INFO CpuInfo; INT Temp; /* Get the CPU Vendor */ - BlArchCpuId(0, 0, CpuInfo); - Temp = CpuInfo[2]; - CpuInfo[2] = CpuInfo[3]; - CpuInfo[3] = Temp; + BlArchCpuId(0, 0, &CpuInfo); + Temp = CpuInfo.Ecx; + CpuInfo.Ecx = CpuInfo.Edx; + CpuInfo.Edx = Temp; /* Check against supported values */ - if (!strncmp((PCHAR)&CpuInfo[1], "GenuineIntel", 12)) + if (!strncmp((PCHAR)&CpuInfo.Ebx, "GenuineIntel", 12)) { return CPU_INTEL; } - if (!strncmp((PCHAR)&CpuInfo[1], "AuthenticAMD", 12)) + if (!strncmp((PCHAR)&CpuInfo.Ebx, "AuthenticAMD", 12)) { return CPU_AMD; } - if (!strncmp((PCHAR)&CpuInfo[1], "CentaurHauls", 12)) + if (!strncmp((PCHAR)&CpuInfo.Ebx, "CentaurHauls", 12)) { return CPU_VIA; } - if (!strncmp((PCHAR)&CpuInfo[1], "CyrixInstead", 12)) + if (!strncmp((PCHAR)&CpuInfo.Ebx, "CyrixInstead", 12)) { return CPU_CYRIX; } - if (!strncmp((PCHAR)&CpuInfo[1], "GenuineTMx86", 12)) + if (!strncmp((PCHAR)&CpuInfo.Ebx, "GenuineTMx86", 12)) { return CPU_TRANSMETA; } - if (!strncmp((PCHAR)&CpuInfo[1], "RiseRiseRise", 12)) + if (!strncmp((PCHAR)&CpuInfo.Ebx, "RiseRiseRise", 12)) { return CPU_RISE; } diff --git a/boot/environ/lib/mm/i386/mmx86.c b/boot/environ/lib/mm/i386/mmx86.c index 38e52df1fd..b72a8983ae 100644 --- a/boot/environ/lib/mm/i386/mmx86.c +++ b/boot/environ/lib/mm/i386/mmx86.c @@ -1101,7 +1101,7 @@ MmArchInitialize ( { NTSTATUS Status; ULONGLONG IncreaseUserVa, PerfCounter, CpuRandom; - INT CpuInfo[4]; + CPU_INFO CpuInfo; /* For phase 2, just map deferred regions */ if (Phase != 1) @@ -1157,10 +1157,10 @@ MmArchInitialize ( if (BlArchIsCpuIdFunctionSupported(1)) { /* Call it */ - BlArchCpuId(1, 0, CpuInfo); + BlArchCpuId(1, 0, &CpuInfo); /* Check if RDRAND is supported */ - if (CpuInfo[2] & 0x40000000) + if (CpuInfo.Ecx & 0x40000000) { EfiPrintf(L"Your CPU can do RDRAND! Good for you!\r\n"); CpuRandom = 0;
