On Mon, Oct 09, 2023 at 01:02:38PM +0200, Philippe Mathieu-Daudé wrote: > Date: Mon, 9 Oct 2023 13:02:38 +0200 > From: Philippe Mathieu-Daudé <phi...@linaro.org> > Subject: [PATCH 5/6] target/i386/hvf: Use x86_cpu in > simulate_[rdmsr|wrmsr]() > X-Mailer: git-send-email 2.41.0 > > We already have 'x86_cpu = X86_CPU(cpu)'. Use the variable > instead of doing another QOM cast with X86_CPU(). > > Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org> > --- > target/i386/hvf/x86_emu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Zhao Liu <zhao1....@intel.com> > > diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c > index ccda568478..af1f205ecf 100644 > --- a/target/i386/hvf/x86_emu.c > +++ b/target/i386/hvf/x86_emu.c > @@ -676,7 +676,7 @@ void simulate_rdmsr(struct CPUState *cpu) > val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET); > break; > case MSR_IA32_APICBASE: > - val = cpu_get_apic_base(X86_CPU(cpu)->apic_state); > + val = cpu_get_apic_base(x86_cpu->apic_state); > break; > case MSR_IA32_UCODE_REV: > val = x86_cpu->ucode_rev; > @@ -776,7 +776,7 @@ void simulate_wrmsr(struct CPUState *cpu) > case MSR_IA32_TSC: > break; > case MSR_IA32_APICBASE: > - cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); > + cpu_set_apic_base(x86_cpu->apic_state, data); > break; > case MSR_FSBASE: > wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data); > -- > 2.41.0 > > >
