In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0. In space_select, the bits that choose the space depend on PSW_W.
Signed-off-by: Richard Henderson <[email protected]> --- target/hppa/cpu.h | 7 +++---- target/hppa/translate.c | 22 +++++++++++++--------- 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 671e43ebd8..1a12b2a186 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -272,7 +272,7 @@ static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, #ifdef CONFIG_USER_ONLY return off; #else - off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); + off &= psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32); return spc | off; #endif } @@ -313,9 +313,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, flags |= env->psw & (PSW_W | PSW_C | PSW_D); flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - *pc = (env->psw & PSW_C - ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) - : env->iaoq_f & -4); + *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); *cs_base = env->iasq_f; /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9d6670f91c..ace6fb0ab2 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -764,6 +764,13 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif +static target_ureg gva_offset_mask(DisasContext *ctx) +{ + return (ctx->tb_flags & PSW_W + ? MAKE_64BIT_MASK(0, 62) + : MAKE_64BIT_MASK(0, 32)); +} + static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { return translator_use_goto_tb(&ctx->base, dest); @@ -1398,7 +1405,8 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) tmp = tcg_temp_new(); spc = tcg_temp_new_tl(); - tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); + /* Extract top 2 bits of the address, shift left 3 for uint64_t index. */ + tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); tcg_gen_andi_reg(tmp, tmp, 030); tcg_gen_trunc_reg_ptr(ptr, tmp); @@ -1415,6 +1423,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, { TCGv_reg base = load_gpr(ctx, rb); TCGv_reg ofs; + TCGv_tl addr; /* Note that RX is mutually exclusive with DISP. */ if (rx) { @@ -1429,18 +1438,13 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, } *pofs = ofs; -#ifdef CONFIG_USER_ONLY - *pgva = (modify <= 0 ? ofs : base); -#else - TCGv_tl addr = tcg_temp_new_tl(); + *pgva = addr = tcg_temp_new_tl(); tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); - if (ctx->tb_flags & PSW_W) { - tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); - } + tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx)); +#ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); } - *pgva = addr; #endif } -- 2.34.1
