[PATCH 00/11] Various updates for the Cadence GEM model

[Luc Michel]

Hi,

This series brings small changes to the Cadence GEM Ethernet model.
There is (almost) no behaviour change.

Patches 1 to 9 replace handcrafted defines with the use of REG32 and
FIELDS macros for register and fields declarations.

Patch 10 fixes PHY accesses so that they are done only on a write to the
PHYMNTNC register (as the real hardware does).

Patch 11 fixes a potential bug on hosts where unsigned would not be 32
bits.

Thanks,

-- 
Luc

Luc Michel (11):
  hw/net/cadence_gem: use REG32 macro for register definitions
  hw/net/cadence_gem: use FIELD for screening registers
  hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
  hw/net/cadence_gem: use FIELD to describe NWCFG register fields
  hw/net/cadence_gem: use FIELD to describe DMACFG register fields
  hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register
    fields
  hw/net/cadence_gem: use FIELD to describe IRQ register fields
  hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
  hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
  hw/net/cadence_gem: perform PHY access on write only
  hw/net/cadence_gem: enforce 32 bits variable size for CRC

 hw/net/cadence_gem.c | 910 ++++++++++++++++++++++++-------------------
 1 file changed, 510 insertions(+), 400 deletions(-)

-- 
2.39.2