From: Thomas Huth <[email protected]> There are a bunch of RISC-V files that are currently not covered by the "get_maintainers.pl" script. Add them to the right sections in MAINTAINERS to fix this problem.
Signed-off-by: Thomas Huth <[email protected]> Acked-by: Christoph Müllner <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Philipp Tomsich <[email protected]> Reviewed-by: LIU Zhiwei <[email protected]> Signed-off-by: Michael Tokarev <[email protected]> --- MAINTAINERS | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 93756ec21a..e80fca855a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -318,8 +318,11 @@ R: Daniel Henrique Barboza <[email protected]> R: Liu Zhiwei <[email protected]> L: [email protected] S: Supported +F: configs/targets/riscv* +F: docs/system/target-riscv.rst F: target/riscv/ F: hw/riscv/ +F: hw/intc/riscv* F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ @@ -331,6 +334,7 @@ L: [email protected] S: Supported F: target/riscv/insn_trans/trans_xthead.c.inc F: target/riscv/xthead*.decode +F: disas/riscv-xthead* RISC-V XVentanaCondOps extension M: Philipp Tomsich <[email protected]> @@ -338,6 +342,7 @@ L: [email protected] S: Maintained F: target/riscv/XVentanaCondOps.decode F: target/riscv/insn_trans/trans_xventanacondops.c.inc +F: disas/riscv-xventana* RENESAS RX CPUs R: Yoshinori Sato <[email protected]> @@ -1527,6 +1532,7 @@ Microchip PolarFire SoC Icicle Kit M: Bin Meng <[email protected]> L: [email protected] S: Supported +F: docs/system/riscv/microchip-icicle-kit.rst F: hw/riscv/microchip_pfsoc.c F: hw/char/mchp_pfsoc_mmuart.c F: hw/misc/mchp_pfsoc_dmc.c @@ -1542,6 +1548,7 @@ Shakti C class SoC M: Vijai Kumar K <[email protected]> L: [email protected] S: Supported +F: docs/system/riscv/shakti-c.rst F: hw/riscv/shakti_c.c F: hw/char/shakti_uart.c F: include/hw/riscv/shakti_c.h @@ -1553,6 +1560,7 @@ M: Bin Meng <[email protected]> M: Palmer Dabbelt <[email protected]> L: [email protected] S: Supported +F: docs/system/riscv/sifive_u.rst F: hw/*/*sifive*.c F: include/hw/*/*sifive*.h @@ -3573,7 +3581,7 @@ M: Alistair Francis <[email protected]> L: [email protected] S: Maintained F: tcg/riscv/ -F: disas/riscv.c +F: disas/riscv.[ch] S390 TCG target M: Richard Henderson <[email protected]> -- 2.39.2
