The following changes since commit c5ea91da443b458352c1b629b490ee6631775cb4:
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2023-09-08 10:06:25 -0400) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230911 for you to fetch changes up to e7a03409f29e2da59297d55afbaec98c96e43e3a: target/riscv: don't read CSR in riscv_csrrw_do64 (2023-09-11 11:45:55 +1000) ---------------------------------------------------------------- First RISC-V PR for 8.2 * Remove 'host' CPU from TCG * riscv_htif Fixup printing on big endian hosts * Add zmmul isa string * Add smepmp isa string * Fix page_check_range use in fault-only-first * Use existing lookup tables for MixColumns * Add RISC-V vector cryptographic instruction set support * Implement WARL behaviour for mcountinhibit/mcounteren * Add Zihintntl extension ISA string to DTS * Fix zfa fleq.d and fltq.d * Fix upper/lower mtime write calculation * Make rtc variable names consistent * Use abi type for linux-user target_ucontext * Add RISC-V KVM AIA Support * Fix riscv,pmu DT node path in the virt machine * Update CSR bits name for svadu extension * Mark zicond non-experimental * Fix satp_mode_finalize() when satp_mode.supported = 0 * Fix non-KVM --enable-debug build * Add new extensions to hwprobe * Use accelerated helper for AES64KS1I * Allocate itrigger timers only once * Respect mseccfg.RLB for pmpaddrX changes * Align the AIA model to v1.0 ratified spec * Don't read the CSR in riscv_csrrw_do64 ---------------------------------------------------------------- Akihiko Odaki (1): target/riscv: Allocate itrigger timers only once Ard Biesheuvel (2): target/riscv: Use existing lookup tables for MixColumns target/riscv: Use accelerated helper for AES64KS1I Conor Dooley (1): hw/riscv: virt: Fix riscv,pmu DT node path Daniel Henrique Barboza (6): target/riscv/cpu.c: do not run 'host' CPU with TCG target/riscv/cpu.c: add zmmul isa string target/riscv/cpu.c: add smepmp isa string target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0 hw/riscv/virt.c: fix non-KVM --enable-debug build hw/intc/riscv_aplic.c fix non-KVM --enable-debug build Dickon Hood (2): target/riscv: Refactor translation of vector-widening instruction target/riscv: Add Zvbb ISA extension support Jason Chien (3): target/riscv: Add Zihintntl extension ISA string to DTS hw/intc: Fix upper/lower mtime write calculation hw/intc: Make rtc variable names consistent Kiran Ostrolenk (4): target/riscv: Refactor some of the generic vector functionality target/riscv: Refactor vector-vector translation macro target/riscv: Refactor some of the generic vector functionality target/riscv: Add Zvknh ISA extension support LIU Zhiwei (3): target/riscv: Fix page_check_range use in fault-only-first target/riscv: Fix zfa fleq.d and fltq.d linux-user/riscv: Use abi type for target_ucontext Lawrence Hunter (2): target/riscv: Add Zvbc ISA extension support target/riscv: Add Zvksh ISA extension support Leon Schuermann (1): target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes Max Chou (3): crypto: Create sm4_subword crypto: Add SM4 constant parameter CK target/riscv: Add Zvksed ISA extension support Nazar Kazakov (4): target/riscv: Remove redundant "cpu_vl == 0" checks target/riscv: Move vector translation checks target/riscv: Add Zvkned ISA extension support target/riscv: Add Zvkg ISA extension support Nikita Shubin (1): target/riscv: don't read CSR in riscv_csrrw_do64 Rob Bradford (1): target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren Robbin Ehn (1): linux-user/riscv: Add new extensions to hwprobe Thomas Huth (2): hw/char/riscv_htif: Fix printing of console characters on big endian hosts hw/char/riscv_htif: Fix the console syscall on big endian hosts Tommy Wu (1): target/riscv: Align the AIA model to v1.0 ratified spec Vineet Gupta (1): riscv: zicond: make non-experimental Weiwei Li (1): target/riscv: Update CSR bits name for svadu extension Yong-Xuan Wang (5): target/riscv: support the AIA device emulation with KVM enabled target/riscv: check the in-kernel irqchip support target/riscv: Create an KVM AIA irqchip target/riscv: update APLIC and IMSIC to support KVM AIA target/riscv: select KVM AIA in riscv virt machine include/crypto/aes.h | 7 + include/crypto/sm4.h | 9 + target/riscv/cpu_bits.h | 8 +- target/riscv/cpu_cfg.h | 9 + target/riscv/debug.h | 3 +- target/riscv/helper.h | 98 +++ target/riscv/kvm_riscv.h | 5 + target/riscv/vector_internals.h | 228 +++++++ target/riscv/insn32.decode | 58 ++ crypto/aes.c | 4 +- crypto/sm4.c | 10 + hw/char/riscv_htif.c | 12 +- hw/intc/riscv_aclint.c | 11 +- hw/intc/riscv_aplic.c | 52 +- hw/intc/riscv_imsic.c | 25 +- hw/riscv/virt.c | 374 ++++++------ linux-user/riscv/signal.c | 4 +- linux-user/syscall.c | 14 +- target/arm/tcg/crypto_helper.c | 10 +- target/riscv/cpu.c | 83 ++- target/riscv/cpu_helper.c | 6 +- target/riscv/crypto_helper.c | 51 +- target/riscv/csr.c | 54 +- target/riscv/debug.c | 15 +- target/riscv/kvm.c | 201 ++++++- target/riscv/pmp.c | 4 + target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 970 ++++++++++++++++++++++++++++++ target/riscv/vector_helper.c | 245 +------- target/riscv/vector_internals.c | 81 +++ target/riscv/insn_trans/trans_rvv.c.inc | 171 +++--- target/riscv/insn_trans/trans_rvvk.c.inc | 606 +++++++++++++++++++ target/riscv/insn_trans/trans_rvzfa.c.inc | 4 +- target/riscv/meson.build | 4 +- 34 files changed, 2785 insertions(+), 652 deletions(-) create mode 100644 target/riscv/vector_internals.h create mode 100644 target/riscv/vcrypto_helper.c create mode 100644 target/riscv/vector_internals.c create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc
