On Thu, Sep 7, 2023 at 8:33 PM LIU Zhiwei <[email protected]> wrote: > > From: LIU Zhiwei <[email protected]> > > Signed-off-by: LIU Zhiwei <[email protected]> > --- > include/qemu/timer.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/include/qemu/timer.h b/include/qemu/timer.h > index 9a91cb1248..105767c195 100644 > --- a/include/qemu/timer.h > +++ b/include/qemu/timer.h > @@ -979,6 +979,25 @@ static inline int64_t cpu_get_host_ticks(void) > return cur - ofs; > } > > +#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 32 > +static inline int64_t cpu_get_host_ticks(void) > +{ > + uint32_t lo, hi; > + asm volatile("RDCYCLE %0\n\t" > + "RDCYCLEH %1" > + : "=r"(lo), "=r"(hi)); > + return lo | (uint64_t)hi << 32; > +} > + > +#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen > 32 > +static inline int64_t cpu_get_host_ticks(void) > +{ > + int64_t val; > + > + asm volatile("RDCYCLE %0" : "=r"(val)); > + return val; > +} > +
rdcycle won't be accessible from the user space directly in the future. rdcycle will be accessible via perf similar to other architectures from the next kernel release [1]. rdtime must be used to compute the host ticks if the host is a riscv. This is the equivalent of rdtsc in x86. [1] https://lore.kernel.org/lkml/CAP-5=fVcMg7TL6W_jH61PW6dYMobuTs13d4JDuTAx=mxj+p...@mail.gmail.com/T/#md852c28f4070212973b796c232ecd37dc1c6cb2b > #else > /* The host CPU doesn't have an easily accessible cycle counter. > Just return a monotonically increasing value. This will be > -- > 2.17.1 > > -- Regards, Atish
