Peter Maydell <[email protected]> writes:
> On Wed, 22 Feb 2023 at 11:01, Alex Bennée <[email protected]> wrote: >> >> This is a mandatory feature for Armv8.1 architectures but we don't >> state the feature clearly in our emulation list. While checking verify >> our cortex-a76 model matches up with the current TRM by breaking out >> the long form isar into a more modern readable FIELD_DP code. >> >> Signed-off-by: Alex Bennée <[email protected]> >> --- >> docs/system/arm/emulation.rst | 1 + >> target/arm/cpu64.c | 29 ++++++++++++++++++++++++++--- >> target/arm/cpu_tcg.c | 2 +- >> 3 files changed, 28 insertions(+), 4 deletions(-) >> >> diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst >> index 2062d71261..2c4fde5eef 100644 >> --- a/docs/system/arm/emulation.rst >> +++ b/docs/system/arm/emulation.rst >> @@ -14,6 +14,7 @@ the following architecture extensions: >> - FEAT_BBM at level 2 (Translation table break-before-make levels) >> - FEAT_BF16 (AArch64 BFloat16 instructions) >> - FEAT_BTI (Branch Target Identification) >> +- FEAT_CRC32 (CRC32 instruction) >> - FEAT_CSV2 (Cache speculation variant 2) >> - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) >> - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) > > Would you mind resubmitting a version of this patch that just > fixes this documentation error and doesn't also do the other > stuff that caused this patch to not get through code review? Sent [email protected] -- Alex Bennée Virtualisation Tech Lead @ Linaro
