On Tue, Jul 11, 2023 at 10:20 PM Philippe Mathieu-Daudé <[email protected]> wrote: > > riscv_cpu_do_interrupt() is not reachable on user emulation. > > Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.h | 5 +++-- > target/riscv/cpu_helper.c | 7 ++----- > 2 files changed, 5 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index dba78db644..0602b948d4 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -416,7 +416,6 @@ extern const char * const riscv_int_regnamesh[]; > extern const char * const riscv_fpr_regnames[]; > > const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); > -void riscv_cpu_do_interrupt(CPUState *cpu); > int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, > int cpuid, DumpState *s); > int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, > @@ -449,6 +448,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, > Error **errp); > #define cpu_mmu_index riscv_cpu_mmu_index > > #ifndef CONFIG_USER_ONLY > +void riscv_cpu_do_interrupt(CPUState *cpu); > void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, > vaddr addr, unsigned size, > MMUAccessType access_type, > @@ -472,7 +472,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, > uint32_t priv, > void *rmw_fn_arg); > > RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); > -#endif > +#endif /* !CONFIG_USER_ONLY */ > + > void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); > > void riscv_translate_init(void); > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 0adde26321..597c47bc56 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -1579,7 +1579,6 @@ static target_ulong > riscv_transformed_insn(CPURISCVState *env, > > return xinsn; > } > -#endif /* !CONFIG_USER_ONLY */ > > /* > * Handle Traps > @@ -1589,8 +1588,6 @@ static target_ulong > riscv_transformed_insn(CPURISCVState *env, > */ > void riscv_cpu_do_interrupt(CPUState *cs) > { > -#if !defined(CONFIG_USER_ONLY) > - > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > bool write_gva = false; > @@ -1783,6 +1780,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > env->two_stage_lookup = false; > env->two_stage_indirect_lookup = false; > -#endif > - cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ > } > + > +#endif /* !CONFIG_USER_ONLY */ > -- > 2.38.1 > >
