The following changes since commit 7efd65423ab22e6f5890ca08ae40c84d6660242f:
Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu into staging (2023-06-14 05:28:51 +0200) are available in the Git repository at: https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230616 for you to fetch changes up to 505aa8d8f29b79fcef77563bb4124208badbd8d4: target/loongarch: Fix CSR.DMW0-3.VSEG check (2023-06-16 17:58:46 +0800) ---------------------------------------------------------------- pull-loongarch-20230616 * Fix CSR.DMW0-3.VSEG check * Add cpu arch_id support * Set physical cpuid route for LoongArch ipi device * Add numa support * Supplement cpu topology arguments ---------------------------------------------------------------- Jiajie Chen (1): target/loongarch: Fix CSR.DMW0-3.VSEG check Tianrui Zhao (4): hw/loongarch/virt: Add cpu arch_id support hw/intc: Set physical cpuid route for LoongArch ipi device hw/loongarch: Add numa support hw/loongarch: Supplement cpu topology arguments hw/intc/loongarch_ipi.c | 44 +++++++++++-- hw/loongarch/Kconfig | 1 + hw/loongarch/acpi-build.c | 78 ++++++++++++++++++----- hw/loongarch/virt.c | 144 ++++++++++++++++++++++++++++++++++++++---- target/loongarch/cpu.h | 2 + target/loongarch/tlb_helper.c | 4 +- 6 files changed, 235 insertions(+), 38 deletions(-)
