On 6/6/23 08:33, Mark Cave-Ayland wrote:
On 05/06/2023 13:43, Philippe Mathieu-Daudé wrote:
On 4/6/23 15:14, Mark Cave-Ayland wrote:
The current use of aliased memory regions causes us 2 problems:
firstly the
output of "info qom-tree" is absolutely huge and difficult to read, and
secondly we have already reached the internal limit for memory
regions as
adding any new memory region into the mac-io region causes QEMU to
assert
with "phys_section_add: Assertion `map->sections_nb < TARGET_PAGE_SIZE'
failed".
Implement the mac-io region aliasing using a single IO memory region
that
applies IO_SLICE_MASK representing the maximum size of the aliased
region and
then forwarding the access to the existing mac-io memory region using
the
address space API.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Laurent Vivier <[email protected]>
---
hw/m68k/q800.c | 100 +++++++++++++++++++++++++++++++++--------
include/hw/m68k/q800.h | 1 +
2 files changed, 82 insertions(+), 19 deletions(-)
Out of curiosity, is mac-io an I/O bus, rather than a MMIO device?
Well for PPC it is currently modelled as a bus, but having worked on the
q800 machine which is the forerunner to the integrated PPC CUDA/PMU
version my best guess now is that it is an MMIO device with partial
address decoding.
Hmm OK... Cc me if you find more doc in future work, I am interested
to understand.
Thanks,
Phil.
