Re: [PATCH 2/4] target/riscv: Remove check on mode for MPRV

[Daniel Henrique Barboza]

On 5/29/23 09:17, Weiwei Li wrote:

Normally, MPRV can be set to 1 only in M mode (It will be cleared
when returning to lower-privilege mode by MRET/SRET).

Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>
---

Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>

  target/riscv/cpu_helper.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bd892c05d4..45baf95c77 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -44,7 +44,7 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
      if (!ifetch) {
          uint64_t status = env->mstatus;

- if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) {

+        if (get_field(status, MSTATUS_MPRV)) {
              mode = get_field(env->mstatus, MSTATUS_MPP);
              virt = get_field(env->mstatus, MSTATUS_MPV) &&
                     (mode != PRV_M);