On 5/2/23 17:11, Peter Maydell wrote:
On Tue, 25 Apr 2023 at 20:32, Richard Henderson
<[email protected]> wrote:
v1:
https://lore.kernel.org/qemu-devel/[email protected]/
v2:
https://lore.kernel.org/qemu-devel/[email protected]/
Based-on: [email protected]
("[PATCH v3 00/57] tcg: Simplify calls to load/store helpers")
The main objective here is to support Arm FEAT_LSE2, which says that any
single memory access that does not cross a 16-byte boundary is atomic.
This is the MO_ATOM_WITHIN16 control.
While I'm touching all of this, a secondary objective is to handle the
atomicity of the IBM machines. Both Power and s390x treat misaligned
accesses as atomic on the lsb of the pointer. For instance, an 8-byte
access at ptr % 8 == 4 will appear as two atomic 4-byte accesses, and
ptr % 4 == 2 will appear as four 3-byte accesses.
I hope you mean "four 2-byte accesses", although I'm never
quite sure how odd s390x can get :-)
Heh. Yes, of course.
r~
