Use this to record the default atomicity of memory operations. Set it to MO_ATOM_WITHIN16 if FEAT_LSE2 applies.
Signed-off-by: Richard Henderson <[email protected]> --- target/arm/translate.h | 14 +++++++++++--- target/arm/translate-a64.c | 4 ++++ target/arm/translate.c | 1 + 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 3717824b75..809479f9b7 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -54,6 +54,7 @@ typedef struct DisasContext { bool eci_handled; int sctlr_b; MemOp be_data; + MemOp atom_data; #if !defined(CONFIG_USER_ONLY) int user; #endif @@ -556,10 +557,10 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) /** * finalize_memop: * @s: DisasContext - * @opc: size+sign+align of the memory operation + * @opc: size+sign+align+atomicity of the memory operation * - * Build the complete MemOp for a memory operation, including alignment - * and endianness. + * Build the complete MemOp for a memory operation, including alignment, + * endianness, and atomicity. * * If (op & MO_AMASK) then the operation already contains the required * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally @@ -568,12 +569,19 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) * In the latter case, there are configuration bits that require alignment, * and this is applied here. Note that there is no way to indicate that * no alignment should ever be enforced; this must be handled manually. + * + * If (op & MO_ATOM_MASK) or (op & MO_ATMAX_MASK) then the operation already + * contains the required atomicity, e.g. for AccType_VEC. Otherwise, apply + * atomicity for AccType_NORMAL. */ static inline MemOp finalize_memop(DisasContext *s, MemOp opc) { if (s->align_mem && !(opc & MO_AMASK)) { opc |= MO_ALIGN; } + if (!(opc & (MO_ATOM_MASK | MO_ATMAX_MASK))) { + opc |= s->atom_data; + } return opc | s->be_data; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cd86597172..fa793485c3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14762,6 +14762,10 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, tcg_debug_assert(dc->tbid & 1); #endif + /* Record the atomicity of a single AccType_NORMAL memory access. */ + dc->atom_data = (dc_isar_feature(aa64_lse2, dc) + ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN); + /* Single step state. The code-generation logic here is: * SS_ACTIVE == 0: * generate code with no special handling for single-stepping (except diff --git a/target/arm/translate.c b/target/arm/translate.c index c23a3462bf..552c376050 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9449,6 +9449,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->sme_trap_nonstreaming = EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); } + dc->atom_data = MO_ATOM_IFALIGN; dc->cp_regs = cpu->cp_regs; dc->features = env->features; -- 2.34.1
