On Tue, 24 Jan 2023 at 00:01, Richard Henderson <[email protected]> wrote: > > With FEAT_RME, there are four physical address spaces. > For now, just define the symbols, and mention them in > the same spots as the other Phys indexes in ptw.c. > > Signed-off-by: Richard Henderson <[email protected]> > --- > target/arm/cpu-param.h | 2 +- > target/arm/cpu.h | 17 +++++++++++++++-- > target/arm/ptw.c | 10 ++++++++-- > 3 files changed, 24 insertions(+), 5 deletions(-) > > diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h > index 53cac9c89b..8dfd7a0bb6 100644 > --- a/target/arm/cpu-param.h > +++ b/target/arm/cpu-param.h > @@ -47,6 +47,6 @@ > bool guarded; > #endif > > -#define NB_MMU_MODES 12 > +#define NB_MMU_MODES 14 > > #endif > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 0114e1ed87..21b9afb773 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -3067,8 +3067,10 @@ typedef enum ARMMMUIdx { > ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, > > /* TLBs with 1-1 mapping to the physical address spaces. */ > - ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, > - ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, > + ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, > + ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, > + ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, > + ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, > > /* > * These are not allocated TLBs and are used only for AT system > @@ -3132,6 +3134,17 @@ typedef enum ARMASIdx { > ARMASIdx_TagS = 3, > } ARMASIdx; > > +static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) > +{ > + return ARMMMUIdx_Phys_S + space;
Compile-time asserts that the mmu idxes are in the same order as the ARMSecuritySpace enum values, since we're assuming that here? Otherwise Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
