From: Nazar Kazakov <[email protected]>
Signed-off-by: Nazar Kazakov <[email protected]>
---
target/riscv/cpu.c | 10 +++++++++-
target/riscv/cpu.h | 2 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0da04d0be1..a78d9ae120 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -101,6 +101,8 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb),
+ ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha),
+ ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb),
ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns),
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
@@ -798,13 +800,19 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
* In principle zve*{x,d} would also suffice here, were they supported
* in qemu
*/
- if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkns) &&
+ if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkns || cpu->cfg.ext_zvknha) &&
!(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_v)) {
error_setg(
errp, "Vector crypto extensions require V or Zve* extensions");
return;
}
+ if (cpu->cfg.ext_zvknhb && !(cpu->cfg.ext_zve64f || cpu->cfg.ext_v)) {
+ error_setg(errp,
+ "Zvknhb extension requires V or Zve64f extensions");
+ return;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
cpu->cfg.ext_zhinxmin) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 56008ef9b9..ebee902806 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -462,6 +462,8 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
bool ext_zvkb;
+ bool ext_zvknha;
+ bool ext_zvknhb;
bool ext_zvkns;
bool ext_zmmul;
bool ext_smaia;
--
2.39.1
