On Thu, 1 Dec 2022 at 16:46, Peter Maydell <[email protected]> wrote: > > On Tue, 22 Nov 2022 at 23:25, Zhuojia Shen <[email protected]> > wrote: > > > > In CPUID registers exposed to userspace, some registers were missing > > and some fields were not exposed. This patch aligns exposed ID > > registers and their fields with what the upstream kernel currently > > exposes. > > Thanks; I've applied this to the target-arm-for-8.0 branch that > will become target-arm.next when 7.2 is out.
Hi; unfortunately I had to drop this patch because it causes the 'sysregs' test case in 'make check-tcg' to fail. Once you've built the test cases once, you can run the single test with something like: $ ./build/arm-clang/qemu-aarch64 build/arm-clang/tests/tcg/aarch64-linux-user/sysregs which then will give you the output. It looks like the test is hard-coded to check that an expected set of fields is exposed, so it should be straightforward to update to match what we now intend to provide to the guest. Would you mind respinning this patch to include the update to the test case tests/tcg/aarch64/sysregs.c ? Checking Counter registers ctr_el0 : 0x0000000080038003 cntvct_el0 : 0x0173150270b0beff cntfrq_el0 : 0x0000000003b9aca0 Checking CPUID registers id_aa64isar0_el1 : 0x1021111110212120 !!extra bits!! : 0x1000000000000000 id_aa64isar1_el1 : 0x0011101101211012 !!extra bits!! : 0x0011100100000000 id_aa64mmfr0_el1 : 0xffffffffff000000 !!extra bits!! : 0xffffffff00000000 id_aa64pfr0_el1 : 0x0001000100110011 id_aa64pfr1_el1 : 0x0000000001000321 !!extra bits!! : 0x0000000001000301 id_aa64dfr0_el1 : 0x0000000000000006 id_aa64zfr0_el1 : 0x0110110100110021 (not RAZ!) midr_el1 : 0x00000000000f0510 mpidr_el1 : 0x0000000080000000 Remaining registers should fail id_mmfr0_el1 : 0x00000000deadbeef id_mmfr1_el1 : 0x00000000deadbeef id_mmfr2_el1 : 0x00000000deadbeef id_mmfr3_el1 : 0x00000000deadbeef mvfr0_el1 : 0x00000000deadbeef mvfr1_el1 : 0x00000000deadbeef Extra information leaked to user-space! thanks -- PMM
