Hello Konrad,
Could you please help me to solve it?
Thanks & Regards,
P.Gowrishankar
On Mon, Dec 5, 2022 at 4:26 PM Gowri Shankar <ggowri...@gmail.com> wrote:
> Hi Konrad,
>
> Thanks for your quick response.
>
> Now I want to increment the TTC counter value to enable the system tick.
> How to configure the TTC register to increment it in QEMU.
>
> I found the steps to enable the TTC counter which is below. But not able
> to increment. If possible could you please share the example source code?
>
> 1. Select clock input source, set prescaler value (slcr.MIO_MUX_SEL
> registers, TTC Clock Control register). Ensure TTC is disabled
> (ttc.Counter_Control_x [DIS] = 1) before proceeding with this step.
> 2. Set interval value (Interval register). This step is optional, for
> interval mode only.
> 3. Set match value (Match registers). This step is optional, if matching
> is to be enabled.
> 4. Enable interrupt (Interrupt Enable register). This step is optional, if
> interrupt is to be enabled.
> 5. Enable/disable waveform output, enable/disable matching, set counting
> direction, set mode, enable counter (TTC Counter Control register). This
> step starts the counter.
>
> Thanks & Regards,
> P.Gowrishankar
>
> On Mon, Dec 5, 2022 at 4:07 PM Konrad, Frederic <frederic.kon...@amd.com>
> wrote:
>
>> Hi Philippe,
>> Hi Gowri,
>>
>> The zcu102 has a zynqmp soc object (hw/arm/xlnx-zcu102.c:125):
>>
>> static void xlnx_zcu102_init(MachineState *machine)
>> {
>> ...
>> object_initialize_child(OBJECT(machine), "soc", &s->soc,
>> TYPE_XLNX_ZYNQMP);
>>
>> So the TTCs should work in the ZCU102.
>>
>> Best Regards,
>> Fred
>>
>> -----Original Message-----
>> From: Philippe Mathieu-Daudé <phi...@linaro.org>
>> Sent: 05 December 2022 09:24
>> To: Gowri Shankar <ggowri...@gmail.com>; QEMU Developers <
>> qemu-devel@nongnu.org>; qemu-arm <qemu-...@nongnu.org>
>> Cc: qemu-disc...@nongnu.org; Konrad, Frederic <frederic.kon...@amd.com>;
>> Iglesias, Francisco <francisco.igles...@amd.com>; Alistair Francis <
>> alistair.fran...@wdc.com>
>> Subject: Re: REG: TTC Timer
>>
>> On 22/11/22 12:27, Gowri Shankar wrote:
>> > Hi Team,
>> >
>> > Advance Thanks for Your support.
>> >
>> > Could you please clarify one point here?
>> > I am using a Xilinx ZCU102 machine with QEMU7.1.0.
>> >
>> > I have seen QEMU 7.1.0 release has TTC timers for the Xilinx-zynqmp
>> > SoC model.
>> > url: https://wiki.qemu.org/ChangeLog/7.1
>> > <https://wiki.qemu.org/ChangeLog/7.1>
>> >
>> > In this case, can the ZCU102 machine also use the TTC feature?
>> > If yes and possible, Could you please share the example code snippet?
>> > --
>> > Thanks & Regards,
>> > P. Gowrishankar.
>> > +919944802490
>>
>> Cc'ing qemu-arm@ mailing list and Xilinx ZCU102 machine developers.
>>
>>
>
> --
> Thanks & Regards,
> P. Gowrishankar.
> +919944802490
>
>
>
>
--
Thanks & Regards,
P. Gowrishankar.
+919944802490
