On 01/06/2012 12:37 PM, Igor Mitsyanko wrote:
> On 01/06/2012 12:02 AM, Mark Langsdorf wrote:
>
> Hello, Mark. According to technical specification on Calxeda website,
> highbank SoC has SD 3.0 host controller, are you planning to implement
> it in qemu? I'm asking because I recently have submitted a patch
> implementing SD 2.0 host controller, and it looks like these two
> specifications revisions are not very different from each other.
>
It's a standard SDHCI controller. There was a model submitted by Vincent
Palatin a while back, but I didn't have much luck getting it working and
haven't debugged it further.
SD3.0 vs 2.0 is probably not going to make a difference from a QEMU
point of view.
Rob
>> + if (!cpu_model) {
>> + cpu_model = "cortex-a9";
>> + }
>
> Google said there is only cortexA9-based Highbank SoC version, maybe you
> should just hardcode cpu model?
>
>> + /* Override default RAM size */
>> + if (ram_size == 0x8000000) {
>> + if (sizeof(long) == 8) {
>> + ram_size = 0xff900000;
>> + } else {
>
> This value looks a bit strange, usually DRAM consists of several banks
> 512, 256 (or something like that) megabytes each, I couldn't find what
> DRAM configuration does the actual board have?
