Hi,
This series fix some bugs find from RISU test.
V3:
-drop patch set some instruction result high 32bit 1.
-follow some change from Richard's suggestion.
v2:
-remove patch5 div if x/0 set dividend to 0.
Song Gao (3):
target/loongarch: bstrins.w src register need EXT_NONE
target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags
softfloat: logB(0) should raise divideByZero exception
fpu/softfloat-parts.c.inc | 1 +
target/loongarch/insn_trans/trans_bit.c.inc | 36 +++++++++++--------
.../loongarch/insn_trans/trans_farith.c.inc | 12 +++----
3 files changed, 29 insertions(+), 20 deletions(-)
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2.31.1
