On Thu, Jun 9, 2022 at 12:15 AM Anup Patel <[email protected]> wrote:
>
> The riscv_cpu_realize() sets priv spec verion to v1.12 when it is
typo: version
> when "env->priv_ver == 0" (i.e. default v1.10) because the enum
> value of priv spec v1.10 is zero.
>
> Due to above issue, the sifive_u machine will see priv spec v1.12
> instead of priv spec v1.10.
>
> To fix this issue, we set latest priv spec version (i.e. v1.12)
> for base rv64/rv32 cpu and riscv_cpu_realize() will override priv
> spec version only when "cpu->cfg.priv_spec != NULL".
>
> Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
> Signed-off-by: Anup Patel <[email protected]>
> Reviewed-by: Frank Chang <[email protected]>
> Reviewed-by: Alistair Francis <[email protected]>
> Reviewed-by: Atish Patra <[email protected]>
> ---
> target/riscv/cpu.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
Otherwise,
Reviewed-by: Bin Meng <[email protected]>
