On Tue, 7 Jun 2022 11:56:17 +0100 Jonathan Cameron <[email protected]> wrote:
> Without being able to write these registers, no interleaving is possible. > More refined checks of HDM register state on commit to follow. > > Signed-off-by: Jonathan Cameron <[email protected]> +Cc Ben on current address. Which reminds me - Ben, when you have time please send an update to MAINTAINERS to switch to your preferred email address going forwards. Thanks, Jonathan > --- > v2: (Ben Widawsky) > - Correctly set a tighter write mask for the endpoint devices where this > register has a different use. > > hw/cxl/cxl-component-utils.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > index 7985c9bfca..40a0f752f2 100644 > --- a/hw/cxl/cxl-component-utils.c > +++ b/hw/cxl/cxl-component-utils.c > @@ -154,7 +154,8 @@ static void ras_init_common(uint32_t *reg_state, uint32_t > *write_msk) > reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00; > } > > -static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk) > +static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, > + enum reg_type type) > { > int decoder_count = 1; > int i; > @@ -174,6 +175,12 @@ static void hdm_init_common(uint32_t *reg_state, > uint32_t *write_msk) > write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000; > write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff; > write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff; > + if (type == CXL2_DEVICE) { > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = > 0xf0000000; > + } else { > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = > 0xffffffff; > + } > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff; > } > } >
