This series covers few fixes discovered while trying to detect priv spec version on QEMU virt machine and QEMU sifive_u machine.
These patches can also be found in riscv_priv_version_fixes_v1 branch at: https://github.com/avpatel/qemu.git Anup Patel (3): target/riscv: Don't force update priv spec version to latest target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher target/riscv: Consider priv spec version when generating ISA string target/riscv/cpu.c | 46 ++++++++++++++++++++++------------------- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 2 ++ 3 files changed, 30 insertions(+), 21 deletions(-) -- 2.34.1
