On 4/15/22 20:20, Tomoaki Kawada wrote:
The control register field PSW.U determines which stack pointer register
(ISP or USP) is mapped as R0. In QEMU, this is implemented by having a
value copied between ISP or USP and R0 whenever PSW.U is updated or
access to ISP/USP is made by an mvtc/mvic instruction. However, this
update process was incorrectly omitted in the clrpsw/setpsw (clear/set
PSW) instructions, causing stack pointers to go out-of-sync.
Good catch.
case PSW_U:
+ z = tcg_const_i32(0);
Use tcg_constant_i32(), which does not require the free at the end.
+
+ /* (PSW.U ? USP : ISP) = R0 */
+ tcg_gen_movcond_i32(TCG_COND_NE, cpu_usp,
+ cpu_psw_u, z, cpu_sp, cpu_usp);
+ tcg_gen_movcond_i32(TCG_COND_EQ, cpu_isp,
+ cpu_psw_u, z, cpu_sp, cpu_isp);
Ok.
+ /* Set PSW.U */
tcg_gen_movi_i32(cpu_psw_u, val);
+
+ /* R0 = (PSW.U ? USP : ISP) */
+ tcg_gen_movcond_i32(TCG_COND_NE, cpu_sp,
+ cpu_psw_u, z, cpu_usp, cpu_isp);
You don't need a movcond here, because you know exactly what the new value of psw_u is
during translate: val. This should be an if statement here.
r~
