On Sun, 6 Mar 2022 at 19:40, Richard Henderson <richard.hender...@linaro.org> wrote: > > The order of arguments between ldnt1 and ld1 are swapped in the > architecture, and similarly for stnt1 and st1. Swap them in the > decode so that we have "m" be the vector operand and "n" be the > general operand. > > Fixes: https://gitlab.com/qemu-project/qemu/-/issues/826 > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > ---
Looking at this more closely, I don't think these two fixes are sufficient. In particular, "the operand fields are swapped" is not the only difference here. For LD1 the scalar register can be SP, but for LDNT1 it can be XZR. Our trans_LDNT1_zprz calls trans_LD1_zprz, so it gets this wrong. I'm going to drop both patches for the moment. thanks -- PMM
