On 11/17/2011 02:24 PM, Benoît Canet wrote:
> Signed-off-by: Benoit Canet <benoit.ca...@gmail.com>
>
> /* sh775x interrupt controller tables for sh_intc.c
> @@ -706,30 +714,40 @@ static CPUWriteMemoryFunc * const sh7750_mmct_write[] =
> {
> sh7750_mmct_writel
> };
>
> -SH7750State *sh7750_init(CPUSH4State * cpu)
> +SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
> {
> SH7750State *s;
> - int sh7750_io_memory;
> int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
>
> s = g_malloc0(sizeof(SH7750State));
> s->cpu = cpu;
> s->periph_freq = 60000000; /* 60MHz */
> - sh7750_io_memory = cpu_register_io_memory(sh7750_mem_read,
> - sh7750_mem_write, s,
> - DEVICE_NATIVE_ENDIAN);
> - cpu_register_physical_memory_offset(0x1f000000, 0x1000,
> - sh7750_io_memory, 0x1f000000);
> - cpu_register_physical_memory_offset(0xff000000, 0x1000,
> - sh7750_io_memory, 0x1f000000);
> - cpu_register_physical_memory_offset(0x1f800000, 0x1000,
> - sh7750_io_memory, 0x1f800000);
> - cpu_register_physical_memory_offset(0xff800000, 0x1000,
> - sh7750_io_memory, 0x1f800000);
> - cpu_register_physical_memory_offset(0x1fc00000, 0x1000,
> - sh7750_io_memory, 0x1fc00000);
> - cpu_register_physical_memory_offset(0xffc00000, 0x1000,
> - sh7750_io_memory, 0x1fc00000);
> + memory_region_init_io(&s->iomem, &sh7750_mem_ops, s,
> + "memory", 0x1fe00000);
Any size >= 0x1fc01000 will work here, why did you pick px1fe00000?
just curious.
I see serial starts at that address, but note that even a larger size
won't interfere, since we never add anything to sysmem at that address.
Anyway, no need to change the patch, since it will work just fine.
--
error compiling committee.c: too many arguments to function
