On 14 November 2011 09:39, Bertrand Cachet <[email protected]> wrote: > @@ -977,6 +977,15 @@ static void lan9118_writel(void *opaque, > target_phys_addr_t offset, > s->pmt_ctrl &= ~0x34e; > s->pmt_ctrl |= (val & 0x34e); > break; > + case CSR_BYTE_TEST: > + /* Even if this register is marked ReadOnly in the datasheet, > + a write to this register will wake up the device when > + PM_MODE is currently in D1 or D2 mode. > + > + As Power Modes are not handled in this driver, we will > + leave this case with no implementation. > + */ > + break; > case CSR_GPIO_CFG: > /* Probably just enabling LEDs. */ > s->gpio_cfg = val & 0x7777071f;
Having thought about this a little, I think we should have the code to modify the pmt_ctrl register here, but with a comment that explains that this is currently a no-op since we are always in power mode D0. There should also be a second patch in the series that corrects the handling for the other RO and WO registers (which should be read as zero and writes ignored, as per the datasheet). -- PMM
