On Thu, Jan 13, 2022 at 11:56 AM Weiwei Li <[email protected]> wrote: > > Co-authored-by: ardxwe <[email protected]> > Signed-off-by: Weiwei Li <[email protected]> > Signed-off-by: Junqiang Wang <[email protected]> > Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index fc3ec5bca1..d5e772b2b8 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -685,6 +685,11 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), > DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > > + DEFINE_PROP_BOOL("Zdinx", RISCVCPU, cfg.ext_zdinx, false), > + DEFINE_PROP_BOOL("Zfinx", RISCVCPU, cfg.ext_zfinx, false), > + DEFINE_PROP_BOOL("Zhinx", RISCVCPU, cfg.ext_zhinx, false), > + DEFINE_PROP_BOOL("Zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), > + > /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > /* ePMP 0.9.3 */ > -- > 2.17.1 > >
