> -----Original Message----- > From: Alistair Francis [mailto:[email protected]] > Sent: Tuesday, January 11, 2022 7:07 AM > To: Jiangyifei <[email protected]> > Cc: [email protected] Developers <[email protected]>; open > list:RISC-V <[email protected]>; [email protected]; open > list:Overall <[email protected]>; [email protected]; Anup Patel > <[email protected]>; Palmer Dabbelt <[email protected]>; Alistair > Francis <[email protected]>; Bin Meng <[email protected]>; > Fanliang (EulerOS) <[email protected]>; Wubin (H) > <[email protected]>; Wanghaibin (D) <[email protected]>; > wanbo (G) <[email protected]>; limingwang (A) > <[email protected]>; Anup Patel <[email protected]> > Subject: Re: [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers > > On Mon, Jan 10, 2022 at 11:57 AM Yifei Jiang via <[email protected]> > wrote: > > > > Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl > > > > Signed-off-by: Yifei Jiang <[email protected]> > > Signed-off-by: Mingwang Li <[email protected]> > > Reviewed-by: Alistair Francis <[email protected]> > > Reviewed-by: Anup Patel <[email protected]> > > --- > > target/riscv/kvm.c | 104 > > ++++++++++++++++++++++++++++++++++++++++++++- > > 1 file changed, 103 insertions(+), 1 deletion(-) > > > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index > > 6d4df0ef6d..e695b91dc7 100644 > > --- a/target/riscv/kvm.c > > +++ b/target/riscv/kvm.c > > @@ -73,6 +73,14 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, > uint64_t type, uint64_t idx > > } \ > > } while(0) > > > > +#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ > > + do { \ > > + int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ > > + if (ret) { \ > > + return ret; \ > > + } \ > > + } while(0) > > This fails checkpatch. I know there is lots of QEMU code like this, but it > probably > should be `while (0)` to keep checkpatch happy. > > Please run checkpatch on all the patches. > > Alistair
OK, it will be modified in the next series. Yifei
