On Mon, Jan 10, 2022 at 04:23:47PM +0800, Tian, Kevin wrote:
> > From: Zhong, Yang <yang.zh...@intel.com>
> > Sent: Friday, January 7, 2022 5:31 PM
> >
> > From: Jing Liu <jing2....@intel.com>
> >
> > AMX XTILECFG and XTILEDATA are managed by XSAVE feature
> > set. State component 17 is used for 64-byte TILECFG register
> > (XTILECFG state) and component 18 is used for 8192 bytes
> > of tile data (XTILEDATA state).
>
> to be consistent, "tile data" -> "TILEDATA"
>
> >
> > Add AMX feature bits to x86_ext_save_areas array to set
> > up AMX components. Add structs that define the layout of
> > AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
> > structs sizes.
> >
> > Signed-off-by: Jing Liu <jing2....@intel.com>
> > Signed-off-by: Yang Zhong <yang.zh...@intel.com>
> > ---
> > target/i386/cpu.h | 16 +++++++++++++++-
> > target/i386/cpu.c | 8 ++++++++
> > 2 files changed, 23 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> > index 7f9700544f..768a8218be 100644
> > --- a/target/i386/cpu.h
> > +++ b/target/i386/cpu.h
> > @@ -537,6 +537,8 @@ typedef enum X86Seg {
> > #define XSTATE_ZMM_Hi256_BIT 6
> > #define XSTATE_Hi16_ZMM_BIT 7
> > #define XSTATE_PKRU_BIT 9
> > +#define XSTATE_XTILE_CFG_BIT 17
> > +#define XSTATE_XTILE_DATA_BIT 18
> >
> > #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
> > #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
> > @@ -1343,6 +1345,16 @@ typedef struct XSavePKRU {
> > uint32_t padding;
> > } XSavePKRU;
> >
> > +/* Ext. save area 17: AMX XTILECFG state */
> > +typedef struct XSaveXTILE_CFG {
>
> remove "_"?
>
> > + uint8_t xtilecfg[64];
> > +} XSaveXTILE_CFG;
> > +
> > +/* Ext. save area 18: AMX XTILEDATA state */
> > +typedef struct XSaveXTILE_DATA {
>
> ditto
>
Thanks Kevin, I will update this in new version.
Yang
